/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIPeepholeSDWA.cpp | 93 bool isConvertibleToSDWA(MachineInstr &MI, const GCNSubtarget &ST) const; 95 const GCNSubtarget &ST) const; 97 void legalizeScalarOperands(MachineInstr &MI, const GCNSubtarget &ST) const; 884 const GCNSubtarget &ST) const { 941 const GCNSubtarget &ST) const { 954 if (!ST.hasSDWAOmod() && TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) 958 if (!ST.hasSDWASdst()) { 965 if (!ST.hasSDWAOutModsVOPC() && 975 if (!ST.hasSDWAMac() && (Opc == AMDGPU::V_FMAC_F16_e32 || 1177 const GCNSubtarget &ST) cons 1208 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); local [all...] |
H A D | R600Packetizer.cpp | 147 R600PacketizerList(MachineFunction &MF, const R600Subtarget &ST, argument 150 TII(ST.getInstrInfo()), 152 VLIW5 = !ST.hasCaymanISA(); 326 const R600Subtarget &ST = Fn.getSubtarget<R600Subtarget>(); local 327 const R600InstrInfo *TII = ST.getInstrInfo(); 332 R600PacketizerList Packetizer(Fn, ST, MLI);
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H A D | SIFormMemoryClauses.cpp | 73 const GCNSubtarget *ST; member in class:__anon2115::SIFormMemoryClauses 253 unsigned Occupancy = MaxPressure.getOccupancy(*ST); 309 ST = &MF.getSubtarget<GCNSubtarget>(); 310 if (!ST->isXNACKEnabled()) 313 const SIInstrInfo *TII = ST->getInstrInfo(); 314 TRI = ST->getRegisterInfo();
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H A D | SIShrinkInstructions.cpp | 227 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>(); local 228 const SIInstrInfo *TII = ST.getInstrInfo(); 315 static bool shrinkScalarLogicOp(const GCNSubtarget &ST, argument 327 !AMDGPU::isInlinableLiteral32(SrcImm->getImm(), ST.hasInv2PiInlineImm())) { 335 } else if (AMDGPU::isInlinableLiteral32(~Imm, ST.hasInv2PiInlineImm())) { 343 } else if (AMDGPU::isInlinableLiteral32(~Imm, ST.hasInv2PiInlineImm())) { 348 if (AMDGPU::isInlinableLiteral32(~Imm, ST.hasInv2PiInlineImm())) { 554 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); local 555 const SIInstrInfo *TII = ST.getInstrInfo(); 556 unsigned VCCReg = ST [all...] |
H A D | SIPreAllocateWWMRegs.cpp | 167 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); local 169 TII = ST.getInstrInfo();
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H A D | AMDGPULegalizerInfo.h | 29 const GCNSubtarget &ST; member in class:llvm::AMDGPULegalizerInfo 32 AMDGPULegalizerInfo(const GCNSubtarget &ST,
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H A D | AMDGPULegalizerInfo.cpp | 165 : ST(ST_) { 264 if (ST.has16BitInsts()) { 350 if (ST.has16BitInsts()) { 351 if (ST.hasVOP3PInsts()) 363 if (ST.hasVOP3PInsts()) { 369 } else if (ST.has16BitInsts()) { 379 if (ST.hasVOP3PInsts()) 384 .clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64); 388 .clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64); 392 .clampScalar(0, ST [all...] |
H A D | GCNSchedStrategy.h | 67 const GCNSubtarget &ST; member in class:llvm::final
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H A D | AMDGPUAnnotateKernelFeatures.cpp | 265 const GCNSubtarget &ST = TM->getSubtarget<GCNSubtarget>(F); local 266 bool HasFlat = ST.hasFlatAddressSpace(); 267 bool HasApertureRegs = ST.hasApertureRegs();
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H A D | SIInsertWaitcnts.cpp | 198 WaitcntBrackets(const GCNSubtarget *SubTarget) : ST(SubTarget) { 352 const GCNSubtarget *ST = nullptr; member in class:__anon2116::WaitcntBrackets 370 const GCNSubtarget *ST = nullptr; member in class:__anon2116::SIInsertWaitcnts 748 !ST->hasFlatLgkmVMemCountInOrder()) { 1062 !ST->hasAutoWaitcntBeforeBarrier()) { 1069 if (readsVCCZ(MI) && ST->hasReadVCCZBug()) { 1179 assert(ST->hasVscnt()); 1230 if (!ST->hasVscnt()) 1255 if (!ST->hasVscnt()) 1265 if (ST [all...] |
H A D | SIWholeQuadMode.cpp | 152 const GCNSubtarget *ST; member in class:__anon2132::SIWholeQuadMode 634 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ? 639 unsigned Exec = ST->isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; 640 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ? 655 unsigned Exec = ST->isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; 660 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ? 687 ST->isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC) 901 ST = &MF.getSubtarget<GCNSubtarget>(); 903 TII = ST->getInstrInfo(); 910 unsigned Exec = ST [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | Mips16HardFloat.cpp | 77 StructType *ST = cast<StructType>(T); local 78 if (ST->getNumElements() != 2) 80 if ((ST->getElementType(0)->isFloatTy()) && 81 (ST->getElementType(1)->isFloatTy())) 83 if ((ST->getElementType(0)->isDoubleTy()) && 84 (ST->getElementType(1)->isDoubleTy()))
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H A D | Mips16FrameLowering.cpp | 178 llvm::createMips16FrameLowering(const MipsSubtarget &ST) { argument 179 return new Mips16FrameLowering(ST);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/ |
H A D | Type.cpp | 351 StructType *ST; local 361 ST = new (Context.pImpl->Alloc) StructType(Context); 362 ST->setSubclassData(SCDB_IsLiteral); // Literal struct. 363 ST->setBody(ETypes, isPacked); 364 *Insertion.first = ST; 367 ST = *Insertion.first; 370 return ST; 442 StructType *ST = new (Context.pImpl->Alloc) StructType(Context); local 444 ST->setName(Name); 445 return ST; 454 StructType *ST = create(Context, Name); local [all...] |
/freebsd-11-stable/sys/i386/i386/ |
H A D | db_disasm.c | 85 #define ST 31 /* FP stack top */ macro 431 /*0*/ { "fadd", SNGL, op2(STI,ST), 0 }, 432 /*1*/ { "fmul", SNGL, op2(STI,ST), 0 }, 433 /*2*/ { "fcom", SNGL, op2(STI,ST), 0 }, 434 /*3*/ { "fcomp", SNGL, op2(STI,ST), 0 }, 435 /*4*/ { "fsub", SNGL, op2(STI,ST), 0 }, 436 /*5*/ { "fsubr", SNGL, op2(STI,ST), 0 }, 437 /*6*/ { "fdiv", SNGL, op2(STI,ST), 0 }, 438 /*7*/ { "fdivr", SNGL, op2(STI,ST), 0 }, 475 /*0*/ { "fadd", DBLR, op2(ST,ST [all...] |
/freebsd-11-stable/sys/amd64/amd64/ |
H A D | db_disasm.c | 99 #define ST 31 /* FP stack top */ macro 505 /*0*/ { "fadd", SNGL, op2(STI,ST), 0 }, 506 /*1*/ { "fmul", SNGL, op2(STI,ST), 0 }, 507 /*2*/ { "fcom", SNGL, op2(STI,ST), 0 }, 508 /*3*/ { "fcomp", SNGL, op2(STI,ST), 0 }, 509 /*4*/ { "fsub", SNGL, op2(STI,ST), 0 }, 510 /*5*/ { "fsubr", SNGL, op2(STI,ST), 0 }, 511 /*6*/ { "fdiv", SNGL, op2(STI,ST), 0 }, 512 /*7*/ { "fdivr", SNGL, op2(STI,ST), 0 }, 549 /*0*/ { "fadd", DBLR, op2(ST,ST [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VEInstrInfo.cpp | 37 VEInstrInfo::VEInstrInfo(VESubtarget &ST) argument 39 Subtarget(ST) {}
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H A D | VEFrameLowering.h | 24 explicit VEFrameLowering(const VESubtarget &ST);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCBoolRetToInt.cpp | 93 Type *IntTy = ST->isPPC64() ? Type::getInt64Ty(V->getContext()) 196 ST = TM.getSubtargetImpl(F); 277 const PPCSubtarget *ST; member in class:__anon2787::PPCBoolRetToInt
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MacroFusion.cpp | 171 const TargetSubtargetInfo &ST = DAG.MF.getSubtarget(); local 174 if (!shouldScheduleAdjacent(TII, ST, nullptr, AnchorMI)) 190 !shouldScheduleAdjacent(TII, ST, DepMI, AnchorMI))
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/freebsd-11-stable/contrib/llvm-project/clang/utils/TableGen/ |
H A D | MveEmitter.cpp | 959 const VectorType *getVectorType(const ScalarType *ST, unsigned Lanes) { 960 std::tuple<ScalarTypeKind, unsigned, unsigned> key(ST->kind(), 961 ST->sizeInBits(), Lanes); 963 VectorTypes[key] = std::make_unique<VectorType>(ST, Lanes); 966 const VectorType *getVectorType(const ScalarType *ST) { 967 return getVectorType(ST, 128 / ST->sizeInBits()); 1142 if (const auto *ST = dyn_cast<ScalarType>(CastType)) { 1143 if (!ST->requiresFloat()) { 1146 ST, Ar 1451 const ScalarType *ST = kv.second.get(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/xray/ |
H A D | xray_segmented_array.h | 597 auto ST = Tail; variable 598 SFH->Prev = ST; 599 ST->Next = Freelist; 600 ST->Prev = &SentinelSegment; 603 Freelist = ST;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 488 StoreSDNode *ST = cast<StoreSDNode>(Op); local 489 assert(!ST->isTruncatingStore() && "Unexpected store type"); 490 assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT"); 493 ST->getMemoryVT(), *ST->getMemOperand())) 496 SDValue Chain = ST->getChain(); 497 SDValue BasePtr = ST->getBasePtr(); 498 SDValue Value = ST->getValue(); 501 if (ST->getAlignment() == 2) { 506 Chain, dl, Low, BasePtr, ST 1782 StoreSDNode *ST = cast<StoreSDNode>(N); local [all...] |
/freebsd-11-stable/usr.sbin/makefs/cd9660/ |
H A D | iso9660_rrip.c | 210 struct ISO_SUSP_ATTRIBUTES *temp, *pre_ce, *last, *CE, *ST; local 215 /* Allow 4 bytes for "ST" record. */ 262 /* An ST entry is needed */ 264 ST = cd9660node_susp_create_node(SUSP_TYPE_SUSP, 265 SUSP_ENTRY_SUSP_ST, "ST", SUSP_LOC_ENTRY); 266 cd9660_susp_st(ST, node); 268 TAILQ_INSERT_AFTER(&node->head, last, ST, rr_ll); 270 TAILQ_INSERT_HEAD(&node->head, ST, rr_ll); 271 last = ST; 306 * ST [all...] |
/freebsd-11-stable/contrib/binutils/opcodes/ |
H A D | i386-dis.c | 4115 #define ST { OP_ST, 0 } macro 4131 { "fadd", { ST, STi } }, 4132 { "fmul", { ST, STi } }, 4135 { "fsub", { ST, STi } }, 4136 { "fsubr", { ST, STi } }, 4137 { "fdiv", { ST, STi } }, 4138 { "fdivr", { ST, STi } }, 4153 { "fcmovb", { ST, STi } }, 4154 { "fcmove", { ST, STi } }, 4155 { "fcmovbe",{ ST, ST [all...] |