/freebsd-11-stable/sys/contrib/dev/acpica/components/executer/ |
H A D | exresop.c | 235 * PARAMETERS: Opcode - Opcode being interpreted 254 UINT16 Opcode, 268 ACPI_FUNCTION_TRACE_U32 (ExResolveOperands, Opcode); 271 OpInfo = AcpiPsGetOpcodeInfo (Opcode); 281 Opcode)); 287 "Opcode %X [%s] RequiredOperandTypes=%8.8X\n", 288 Opcode, OpInfo->Name, ArgTypes)); 459 if ((Opcode == AML_STORE_OP) && 836 AcpiPsGetOpcodeName (Opcode), WalkStat 253 AcpiExResolveOperands( UINT16 Opcode, ACPI_OPERAND_OBJECT **StackPtr, ACPI_WALK_STATE *WalkState) argument [all...] |
H A D | exoparg6.c | 341 AcpiPsGetOpcodeName (WalkState->Opcode)); 344 switch (WalkState->Opcode) 441 WalkState->Opcode));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCMIPeephole.cpp | 164 unsigned Opcode = MI->getOpcode(); local 165 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec || 166 Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec) 169 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) && 173 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || 174 Opcode [all...] |
H A D | PPCHazardRecognizers.cpp | 278 PPCHazardRecognizer970::GetInstrType(unsigned Opcode, argument 282 const MCInstrDesc &MCID = DAG.TII->get(Opcode); 333 unsigned Opcode = MI->getOpcode(); local 336 GetInstrType(Opcode, isFirst, isSingle, isCracked, 370 if (HasCTRSet && Opcode == PPC::BCTRL) 391 unsigned Opcode = MI->getOpcode(); local 394 GetInstrType(Opcode, isFirst, isSingle, isCracked, 399 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true;
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/ |
H A D | ConstantFolding.h | 77 Constant *ConstantFoldUnaryOpOperand(unsigned Opcode, Constant *Op, 83 Constant *ConstantFoldBinaryOpOperands(unsigned Opcode, Constant *LHS, 94 Constant *ConstantFoldCastOperand(unsigned Opcode, Constant *C, Type *DestTy,
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | Utils.h | 136 /// Opcode. Also try to do trivial folding if it's a COPY with 138 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg, 154 Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const unsigned Op1, 158 Optional<APInt> ConstantFoldExtOp(unsigned Opcode, const unsigned Op1,
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H A D | LegalizerInfo.h | 104 unsigned Opcode; member in struct:llvm::InstrAspect 108 InstrAspect(unsigned Opcode, LLT Type) : Opcode(Opcode), Type(Type) {} argument 109 InstrAspect(unsigned Opcode, unsigned Idx, LLT Type) argument 110 : Opcode(Opcode), Idx(Idx), Type(Type) {} 113 return Opcode == RHS.Opcode && Idx == RHS.Idx && Type == RHS.Type; 122 unsigned Opcode; member in struct:llvm::LegalityQuery 135 LegalityQuery(unsigned Opcode, const ArrayRef<LLT> Types, const ArrayRef<MemDesc> MMODescrs) argument 138 LegalityQuery(unsigned Opcode, const ArrayRef<LLT> Types) argument 469 aliasTo(unsigned Opcode) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.cpp | 107 bool R600InstrInfo::isMov(unsigned Opcode) const { 108 switch(Opcode) { 118 bool R600InstrInfo::isReductionOp(unsigned Opcode) const { 122 bool R600InstrInfo::isCubeOp(unsigned Opcode) const { 123 switch(Opcode) { 133 bool R600InstrInfo::isALUInstr(unsigned Opcode) const { 134 unsigned TargetFlags = get(Opcode).TSFlags; 139 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const { 140 unsigned TargetFlags = get(Opcode).TSFlags; 147 bool R600InstrInfo::isLDSInstr(unsigned Opcode) cons 254 getSelIdx(unsigned Opcode, unsigned SrcIdx) const argument [all...] |
H A D | AMDGPUTargetTransformInfo.h | 175 unsigned Opcode, Type *Ty, 183 unsigned getCFInstrCost(unsigned Opcode); 185 int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index); 214 int getArithmeticReductionCost(unsigned Opcode, 269 unsigned getCFInstrCost(unsigned Opcode); 270 int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.h | 358 bool isEndLoopN(unsigned Opcode) const; 376 bool isNewValue(unsigned Opcode) const; 379 bool isNewValueJump(unsigned Opcode) const; 381 bool isNewValueStore(unsigned Opcode) const; 384 bool isPredicatedNew(unsigned Opcode) const; 386 bool isPredicatedTrue(unsigned Opcode) const; 387 bool isPredicated(unsigned Opcode) const; 388 bool isPredicateLate(unsigned Opcode) const; 389 bool isPredictedTaken(unsigned Opcode) const; 402 bool isValidOffset(unsigned Opcode, in [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCInstrInfo.cpp | 53 static bool isLoad(int Opcode) { argument 54 return Opcode == ARC::LD_rs9 || Opcode == ARC::LDH_rs9 || 55 Opcode == ARC::LDB_rs9; 58 static bool isStore(int Opcode) { argument 59 return Opcode == ARC::ST_rs9 || Opcode == ARC::STH_rs9 || 60 Opcode == ARC::STB_rs9; 70 int Opcode = MI.getOpcode(); local 71 if (isLoad(Opcode)) { 89 int Opcode = MI.getOpcode(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsTargetStreamer.h | 119 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, 121 void emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, 123 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc, 125 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc, 127 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc, 129 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2, 131 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, 133 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, 135 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm, 137 void emitRRIII(unsigned Opcode, unsigne [all...] |
H A D | MipsAsmPrinter.h | 91 void EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg); 93 void EmitInstrRegReg(const MCSubtargetInfo &STI, unsigned Opcode, 96 void EmitInstrRegRegReg(const MCSubtargetInfo &STI, unsigned Opcode, 114 bool isLongBranchPseudo(int Opcode) const;
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H A D | MipsMCInstLower.h | 47 int Opcode) const;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 84 int AArch64TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, argument 95 switch (Opcode) { 205 bool AArch64TTIImpl::isWideningInstruction(Type *DstTy, unsigned Opcode, argument 227 switch (Opcode) { 269 int AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, argument 271 int ISD = TLI->InstructionOpcodeToISD(Opcode); 298 return BaseT::getCastInstrCost(Opcode, Dst, Src); 402 return BaseT::getCastInstrCost(Opcode, Dst, Src); 405 int AArch64TTIImpl::getExtractWithExtendCost(unsigned Opcode, Type *Dst, argument 410 assert((Opcode 460 getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) argument 485 getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, const Instruction *CxtI) argument 598 getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, const Instruction *I) argument 642 getMemoryOpCost(unsigned Opcode, Type *Ty, MaybeAlign Alignment, unsigned AddressSpace, const Instruction *I) argument 680 getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond, bool UseMaskForGaps) argument 903 useReductionIntrinsic(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const argument 928 getArithmeticReductionCost(unsigned Opcode, Type *ValTy, bool IsPairwiseForm) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | BasicTTIImpl.h | 414 unsigned getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy) { argument 416 switch (Opcode) { 434 return BaseT::getOperationCost(Opcode, Ty, OpTy); 631 unsigned Opcode, Type *Ty, 640 int ISD = TLI->InstructionOpcodeToISD(Opcode); 668 ->getArithmeticInstrCost(Opcode, Ty->getScalarType()); 697 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, argument 700 int ISD = TLI->InstructionOpcodeToISD(Opcode); 710 if (Opcode == Instruction::BitCast || Opcode 630 getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None, ArrayRef<const Value *> Args = ArrayRef<const Value *>(), const Instruction *CxtI = nullptr) argument 823 getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) argument 831 getCFInstrCost(unsigned Opcode) argument 836 getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, const Instruction *I) argument 876 getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) argument 883 getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, const Instruction *I = nullptr) argument 915 getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond = false, bool UseMaskForGaps = false) argument 1398 unsigned Opcode = IID == Intrinsic::sadd_with_overflow local 1424 unsigned Opcode = IID == Intrinsic::uadd_with_overflow local 1606 getArithmeticReductionCost(unsigned Opcode, Type *Ty, bool IsPairwise) argument [all...] |
H A D | TargetSchedule.h | 192 unsigned computeInstrLatency(unsigned Opcode) const; 204 double computeReciprocalThroughput(unsigned Opcode) const;
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/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/xray/ |
H A D | xray_mips.cpp | 40 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, 43 return (Opcode | Rs << 21 | Rt << 16 | Imm); 47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, 49 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVTargetTransformInfo.h | 45 int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
H A D | LanaiInstPrinter.h | 58 StringRef Opcode, int AddOffset); 60 StringRef Opcode, int AddOffset);
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/freebsd-11-stable/contrib/llvm-project/clang/lib/AST/Interp/ |
H A D | ByteCodeEmitter.h | 29 enum Opcode : uint32_t; 93 /// Opcode to expression mapping. 101 bool emitOp(Opcode Op, const Tys &... Args, const SourceInfo &L);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiRegisterInfo.cpp | 74 static bool isALUArithLoOpcode(unsigned Opcode) { argument 75 switch (Opcode) { 90 static unsigned getOppositeALULoOpcode(unsigned Opcode) { argument 91 switch (Opcode) { 113 static unsigned getRRMOpcodeVariant(unsigned Opcode) { argument 114 switch (Opcode) { 132 llvm_unreachable("Opcode has no RRM variant");
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/ |
H A D | MCInstPrinter.cpp | 41 StringRef MCInstPrinter::getOpcodeName(unsigned Opcode) const { 42 return MII.getName(Opcode); 109 [](const PatternsForOpcode &L, unsigned Opcode) { 110 return L.Opcode < Opcode; 112 if (It == M.OpToPatterns.end() || It->Opcode != MI->getOpcode())
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.h | 156 int getTwoOperandOpcode(uint16_t Opcode); 157 int getTargetMemOpcode(uint16_t Opcode); 292 // Opcode is the opcode of an instruction that has an address operand, 295 // instruction (which might be Opcode itself) or 0 if no such instruction 297 unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const; 299 // If Opcode is a load instruction that has a LOAD AND TEST form, 301 unsigned getLoadAndTest(unsigned Opcode) const; 309 // If Opcode is a COMPARE opcode for which an associated fused COMPARE AND * 312 unsigned getFusedCompare(unsigned Opcode, 316 // If Opcode i [all...] |
/freebsd-11-stable/contrib/llvm-project/clang/utils/TableGen/ |
H A D | ClangOpcodesEmitter.cpp | 29 : Records(R), Root("Opcode", SMLoc(), R), 89 for (auto *Opcode : Records.getAllDerivedDefinitions(Root.getName())) { 91 StringRef N = Opcode->getValueAsString("Name"); 93 N = Opcode->getName(); 95 EmitEnum(OS, N, Opcode); 96 EmitInterp(OS, N, Opcode); 97 EmitDisasm(OS, N, Opcode); 98 EmitProto(OS, N, Opcode); 99 EmitGroup(OS, N, Opcode); 100 EmitEmitter(OS, N, Opcode); [all...] |