/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.h | 112 int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 118 int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty); 170 bool useReductionIntrinsic(unsigned Opcode, Type *Ty, 196 int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 199 int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 202 int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index); 208 unsigned Opcode, Type *Ty, 216 int getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, 219 int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor,
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H A D | ARMSelectionDAGInfo.h | 23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { argument 24 switch (Opcode) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiTargetTransformInfo.h | 79 unsigned Opcode, Type *Ty, 86 int ISD = TLI->InstructionOpcodeToISD(Opcode); 90 return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info, 101 return 64 * BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info, 78 getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None, ArrayRef<const Value *> Args = ArrayRef<const Value *>(), const Instruction *CxtI = nullptr) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXTargetTransformInfo.cpp | 115 unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, 122 int ISD = TLI->InstructionOpcodeToISD(Opcode); 126 return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info, 139 return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info, 114 getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, const Instruction *CxtI) argument
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H A D | NVPTXISelDAGToDAG.cpp | 914 Optional<unsigned> Opcode; 918 Opcode = pickOpcodeForVT( 922 if (!Opcode) 927 NVPTXLD = CurDAG->getMachineNode(Opcode.getValue(), dl, TargetVT, 931 Opcode = pickOpcodeForVT(TargetVT, NVPTX::LD_i8_asi, NVPTX::LD_i16_asi, 935 if (!Opcode) 940 NVPTXLD = CurDAG->getMachineNode(Opcode.getValue(), dl, TargetVT, 945 Opcode = pickOpcodeForVT( 950 Opcode = pickOpcodeForVT( 954 if (!Opcode) [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
H A D | VPlanSLP.cpp | 92 unsigned Opcode = OriginalInstr->getOpcode(); local 94 if (!all_of(Operands, [Opcode, Width](VPValue *Op) { 96 return I->getOpcode() == Opcode && 121 if (Opcode == Instruction::Load) { 148 if (Opcode == Instruction::Store) 197 unsigned Opcode = cast<VPInstruction>(Values[0])->getOpcode(); local 198 if (any_of(Values, [Opcode](VPValue *V) { 199 return cast<VPInstruction>(V)->getOpcode() != Opcode; 202 return {Opcode}; 244 assert((Mode == OpMode::Load || Mode == OpMode::Opcode) 446 unsigned Opcode; local [all...] |
H A D | LoopVectorizationPlanner.h | 40 VPInstruction *createInstruction(unsigned Opcode, argument 42 VPInstruction *Instr = new VPInstruction(Opcode, Operands); 48 VPInstruction *createInstruction(unsigned Opcode, argument 50 return createInstruction(Opcode, ArrayRef<VPValue *>(Operands)); 115 /// Create an N-ary operation with \p Opcode, \p Operands and set \p Inst as 117 VPValue *createNaryOp(unsigned Opcode, ArrayRef<VPValue *> Operands, argument 119 VPInstruction *NewVPInst = createInstruction(Opcode, Operands); 123 VPValue *createNaryOp(unsigned Opcode, argument 126 return createNaryOp(Opcode, ArrayRef<VPValue *>(Operands), Inst);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | TargetTransformInfo.cpp | 149 int TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty, argument 151 int Cost = TTIImpl->getOperationCost(Opcode, Ty, OpTy); 453 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, argument 456 int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty); 467 int TargetTransformInfo::getIntImmCostInst(unsigned Opcode, unsigned Idx, argument 469 int Cost = TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty); 595 unsigned Opcode, Type *Ty, OperandValueKind Opd1Info, 600 Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo, Args, CxtI); 612 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst, argument 614 assert ((I == nullptr || I->getOpcode() == Opcode) 594 getArithmeticInstrCost( unsigned Opcode, Type *Ty, OperandValueKind Opd1Info, OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo, OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, const Instruction *CxtI) const argument 621 getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const argument 635 getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, const Instruction *I) const argument 644 getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const argument 651 getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, const Instruction *I) const argument 662 getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace) const argument 671 getGatherScatterOpCost(unsigned Opcode, Type *DataTy, Value *Ptr, bool VariableMask, unsigned Alignment) const argument 680 getInterleavedMemoryOpCost( unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond, bool UseMaskForGaps) const argument 733 getArithmeticReductionCost(unsigned Opcode, Type *Ty, bool IsPairwiseForm) const argument 842 useReductionIntrinsic(unsigned Opcode, Type *Ty, ReductionFlags Flags) const argument 890 ReductionData(ReductionKind Kind, unsigned Opcode, Value *LHS, Value *RHS) argument 894 unsigned Opcode = 0; member in struct:__anon1656::ReductionData 1010 matchPairwiseReduction(const ExtractElementInst *ReduxRoot, unsigned &Opcode, Type *&Ty) argument 1075 matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot, unsigned &Opcode, Type *&Ty) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/ |
H A D | DWARFExpression.cpp | 125 Opcode = Data.getU8(&Offset); 127 Desc = getOpDesc(Opcode); 207 static bool prettyPrintRegisterOp(raw_ostream &OS, uint8_t Opcode, argument 216 if (Opcode == DW_OP_bregx || Opcode == DW_OP_regx) 218 else if (Opcode >= DW_OP_breg0 && Opcode < DW_OP_bregx) 219 DwarfRegNum = Opcode - DW_OP_breg0; 221 DwarfRegNum = Opcode - DW_OP_reg0; 225 if ((Opcode > [all...] |
/freebsd-11-stable/sys/contrib/dev/acpica/components/parser/ |
H A D | psobject.c | 192 WalkState->Opcode = AcpiPsPeekOpcode (&(WalkState->ParserState)); 200 WalkState->OpInfo = AcpiPsGetOpcodeInfo (WalkState->Opcode); 210 WalkState->Opcode = AML_INT_NAMEPATH_OP; 225 WalkState->Opcode, 237 WalkState->Opcode, 263 if (WalkState->Opcode > 0xFF) /* Can only happen if first byte is 0x5B */ 275 AcpiPsGetOpcodeSize (WalkState->Opcode); 315 UnnamedOp->Common.AmlOpcode = WalkState->Opcode; 479 WalkState->OpInfo = AcpiPsGetOpcodeInfo (WalkState->Opcode); 480 Op = AcpiPsAllocOp (WalkState->Opcode, AmlOpStar [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ExpandPseudoInsts.cpp | 131 switch (I->Opcode) 137 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) 147 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) 158 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) 411 unsigned Opcode = MI.getOpcode(); local 412 switch (Opcode) { 440 unsigned Opcode; local 444 case AArch64::ADDWrr: Opcode = AArch64::ADDWrs; break; 445 case AArch64::SUBWrr: Opcode = AArch64::SUBWrs; break; 446 case AArch64::ADDXrr: Opcode [all...] |
/freebsd-11-stable/contrib/libpcap/rpcapd/ |
H A D | win32-svc.c | 68 void WINAPI svc_control_handler(DWORD Opcode) argument 70 switch(Opcode)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/ |
H A D | ConstantFold.h | 46 Constant *ConstantFoldUnaryInstruction(unsigned Opcode, Constant *V); 47 Constant *ConstantFoldBinaryInstruction(unsigned Opcode, Constant *V1,
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/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/PPC64/ |
H A D | EmulateInstructionPPC64.h | 72 struct Opcode { struct in class:lldb_private::EmulateInstructionPPC64 81 Opcode *GetOpcodeForInstruction(uint32_t opcode);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ExpandSpecialInstrs.cpp | 155 unsigned Opcode = BMI->getOpcode(); local 159 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src0)) 162 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src1)) 251 unsigned Opcode = MI.getOpcode(); local 252 switch (Opcode) { 254 Opcode = R600::CUBE_r600_real; 257 Opcode = R600::CUBE_eg_real; 264 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | Mips16ISelDAGToDAG.cpp | 53 unsigned Opcode = Mips::Mflo16; local 54 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag); 58 unsigned Opcode = Mips::Mfhi16; local 59 Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag); 180 unsigned Opcode = Node->getOpcode(); local 190 switch (Opcode) { 197 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips::MultRxRy16); 212 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRRegisterInfo.cpp | 100 int Opcode = MI.getOpcode(); local 103 if ((Opcode != AVR::SUBIWRdK) && (Opcode != AVR::ADIWRdK)) { 114 switch (Opcode) { 160 unsigned Opcode; local 183 Opcode = AVR::ADIWRdK; 190 Opcode = AVR::SUBIWRdK; 196 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg)
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H A D | AVRFrameLowering.cpp | 129 unsigned Opcode = (isUInt<6>(FrameSize)) ? AVR::SBIWRdK : AVR::SUBIWRdK; local 131 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28) 197 unsigned Opcode; local 201 Opcode = AVR::ADIWRdK; 203 Opcode = AVR::SUBIWRdK; 208 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28) 315 unsigned Opcode = I->getOpcode(); local 318 if (Opcode != AVR::STDSPQRr && Opcode != AVR::STDWSPQRr) { 332 if (Opcode 376 unsigned int Opcode = MI->getOpcode(); local 462 int Opcode = MI.getOpcode(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyTargetTransformInfo.h | 59 unsigned Opcode, Type *Ty, 66 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64InstPrinter.cpp | 64 unsigned Opcode = MI->getOpcode(); local 66 if (Opcode == AArch64::SYSxt) 73 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri || 74 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) { 80 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri); 81 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode 310 isTblTbxInstruction(unsigned Opcode, StringRef &Layout, bool &IsTbx) argument 347 unsigned Opcode; member in struct:LdStNInstrDesc 698 getLdStNInstrDesc(unsigned Opcode) argument 711 unsigned Opcode = MI->getOpcode(); local 765 unsigned Opcode = MI->getOpcode(); local 1382 unsigned Opcode = MI->getOpcode(); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.cpp | 178 unsigned Opcode = getOpcodeForOffset( local 181 MI.setDesc(get(Opcode)); 190 unsigned Opcode = SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode; local 191 MI.setDesc(get(Opcode)); 252 unsigned Opcode; local 256 Opcode = SystemZ::RISBHH; 258 Opcode = SystemZ::RISBHL; 260 Opcode = SystemZ::RISBLH; 266 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) 673 unsigned Opcode local 724 unsigned Opcode = MI.getOpcode(); local 840 unsigned Opcode; local 925 interpretAndImmediate(unsigned Opcode) argument 1010 unsigned Opcode = MI.getOpcode(); local 1509 getOpcodeForOffset(unsigned Opcode, int64_t Offset) const argument 1606 getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI) const argument 1744 unsigned Opcode; local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/DebugInfo/DWARF/ |
H A D | DWARFDebugFrame.h | 42 Instruction(uint8_t Opcode) : Opcode(Opcode) {} argument 44 uint8_t Opcode; member in struct:llvm::dwarf::CFIProgram::Instruction 84 void addInstruction(uint8_t Opcode) { argument 85 Instructions.push_back(Instruction(Opcode)); 89 void addInstruction(uint8_t Opcode, uint64_t Operand1) { argument 90 Instructions.push_back(Instruction(Opcode)); 95 void addInstruction(uint8_t Opcode, uint64_t Operand1, uint64_t Operand2) { argument 96 Instructions.push_back(Instruction(Opcode)); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/MCParser/ |
H A D | MCTargetAsmParser.h | 218 // the type of the expected operand. Opcode is the opcode of the encoding. 221 unsigned OperandClass, unsigned Opcode, 227 Result.MissedOperand.Opcode = Opcode; 234 // was not provided. Opcode is the instruction encoding. 236 unsigned Opcode) { 240 Result.TooFewOperands.Opcode = Opcode; 265 // Opcode of the encoding we were trying to match. 268 return MissedOperand.Opcode; 220 getMissedOperand(unsigned OperandError, unsigned OperandClass, unsigned Opcode, unsigned OperandIndex) argument 235 getTooFewOperands(unsigned OperandClass, unsigned Opcode) argument 289 unsigned Opcode; member in struct:llvm::NearMissInfo::MissedOpInfo 296 unsigned Opcode; member in struct:llvm::NearMissInfo::TooFewOperandsInfo [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 300 unsigned Opcode = MI.getOpcode(); local 304 if (End != std::find(OpcodesForSpill, End, Opcode)) { 354 unsigned Opcode = MI.getOpcode(); local 358 if (End != std::find(OpcodesForSpill, End, Opcode)) { 473 unsigned Opcode; local 475 default: Opcode = PPC::NOP; break; 476 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break; 477 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break; 478 case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */ 480 case PPC::DIR_PWR9: Opcode 1203 unsigned Opcode = getStoreOpcodeForSpill(PPC::NoRegister, RC); local 1260 unsigned Opcode = getLoadOpcodeForSpill(PPC::NoRegister, RC); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/ |
H A D | TargetTransformInfo.h | 219 int getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy = nullptr) const; 907 unsigned Opcode, Type *Ty, OperandValueKind Opd1Info = OK_AnyValue, 923 /// zext, etc. If there is an existing instruction that holds Opcode, it 925 int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 930 int getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, 935 int getCFInstrCost(unsigned Opcode) const; 938 /// is an existing instruction that holds Opcode, it may be passed in the 940 int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 945 int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index = -1) const; 948 int getMemoryOpCost(unsigned Opcode, Typ [all...] |