Searched refs:MRI (Results 51 - 75 of 513) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCTargetDesc.h36 const MCRegisterInfo &MRI,
39 const MCRegisterInfo &MRI,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCTargetDesc.h39 const MCRegisterInfo &MRI,
44 const MCRegisterInfo &MRI,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp34 const MCRegisterInfo &MRI; member in class:__anon2613::BPFMCCodeEmitter
40 : MCII(mcii), MRI(mri), IsLittleEndian(IsLittleEndian) {}
75 const MCRegisterInfo &MRI,
77 return new BPFMCCodeEmitter(MCII, MRI, true);
81 const MCRegisterInfo &MRI,
83 return new BPFMCCodeEmitter(MCII, MRI, false);
91 return MRI.getEncodingValue(MO.getReg());
164 Encoding = MRI.getEncodingValue(Op1.getReg());
74 createBPFMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx) argument
80 createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx) argument
H A DBPFInstPrinter.h22 const MCRegisterInfo &MRI)
23 : MCInstPrinter(MAI, MII, MRI) {}
21 BPFInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/MCTargetDesc/
H A DARCInstPrinter.h25 const MCRegisterInfo &MRI)
26 : MCInstPrinter(MAI, MII, MRI) {}
24 ARCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
H A DARCMCTargetDesc.cpp54 static MCAsmInfo *createARCMCAsmInfo(const MCRegisterInfo &MRI, argument
70 const MCRegisterInfo &MRI) {
71 return new ARCInstPrinter(MAI, MII, MRI);
66 createARCMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonInstPrinter.h28 MCRegisterInfo const &MRI)
29 : MCInstPrinter(MAI, MII, MRI), MII(MII) {}
27 HexagonInstPrinter(MCAsmInfo const &MAI, MCInstrInfo const &MII, MCRegisterInfo const &MRI) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMIRVRegNamerUtils.cpp22 Changed = Changed || !MRI.reg_empty(E.first);
23 MRI.replaceRegWith(E.first, E.second);
65 return MRI.getVRegDef(MO.getReg())->getOpcode();
125 std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg));
153 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
154 return RC ? MRI.createVirtualRegister(RC, LowerName)
155 : MRI.createGenericVirtualRegister(MRI.getType(VReg), LowerName);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/MCTargetDesc/
H A DXCoreInstPrinter.h26 const MCRegisterInfo &MRI)
27 : MCInstPrinter(MAI, MII, MRI) {}
25 XCoreInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombiner.h39 MachineRegisterInfo *MRI = nullptr; member in class:llvm::Combiner
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.h28 MipsHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI) argument
29 : MIRBuilder(MIRBuilder), MRI(MRI) {}
43 MachineRegisterInfo &MRI; member in class:llvm::MipsCallLowering::MipsHandler
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEMCTargetDesc.cpp34 static MCAsmInfo *createVEMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, argument
37 unsigned Reg = MRI.getDwarfRegNum(VE::SX11, true);
78 const MCRegisterInfo &MRI) {
79 return new VEInstPrinter(MAI, MII, MRI);
74 createVEMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCTargetDesc.cpp53 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI, argument
58 Register SP = MRI.getDwarfRegNum(RISCV::X2, true);
77 const MCRegisterInfo &MRI) {
78 return new RISCVInstPrinter(MAI, MII, MRI);
73 createRISCVMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCInstrDesc.cpp45 const MCRegisterInfo *MRI) const {
48 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCTargetDesc.h37 const MCRegisterInfo &MRI,
42 const MCRegisterInfo &MRI,
47 const MCRegisterInfo &MRI,
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MCA/
H A DContext.h52 const MCRegisterInfo &MRI; member in class:llvm::mca::Context
56 Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) : MRI(R), STI(S) {}
60 const MCRegisterInfo &getMCRegisterInfo() const { return MRI; }
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVExtract.cpp58 MachineRegisterInfo &MRI);
68 MachineRegisterInfo &MRI) {
71 Register ElemR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
78 MachineInstr *DI = MRI.getVRegDef(ExtIdxR);
90 Register IdxR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
105 MachineRegisterInfo &MRI = MF.getRegInfo(); local
125 Register AddrR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
139 const auto &VecRC = *MRI.getRegClass(VecR);
149 MachineInstr *DefI = MRI.getVRegDef(VecR);
173 unsigned ElemR = genElemLoad(ExtI, BaseR, MRI);
67 genElemLoad(MachineInstr *ExtI, unsigned BaseR, MachineRegisterInfo &MRI) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.h62 const MachineRegisterInfo &MRI);
85 static unsigned getRegKind(unsigned Reg, const MachineRegisterInfo &MRI);
107 mutable const MachineRegisterInfo *MRI = nullptr; member in class:llvm::GCNRPTracker
133 const MachineRegisterInfo &MRI);
190 const MachineRegisterInfo &MRI);
194 const MachineRegisterInfo &MRI);
213 auto &MRI = (*R.begin())->getParent()->getParent()->getRegInfo(); local
216 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
227 MRI.getMaxLaneMaskForVReg(Reg);
253 GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI, argument
[all...]
H A DSIFixSGPRCopies.cpp117 MachineRegisterInfo *MRI; member in class:__anon2111::SIFixSGPRCopies
155 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); local
161 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg())))
170 const MachineRegisterInfo &MRI) {
175 ? MRI.getRegClass(SrcReg)
182 ? MRI.getRegClass(DstReg)
205 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); local
213 for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) {
223 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI
168 getCopyRegClasses(const MachineInstr &Copy, const SIRegisterInfo &TRI, const MachineRegisterInfo &MRI) argument
240 foldVGPRCopyIntoRegSequence(MachineInstr &MI, const SIRegisterInfo *TRI, const SIInstrInfo *TII, MachineRegisterInfo &MRI) argument
[all...]
H A DAMDGPUInstructionSelector.cpp69 MRI = &MF.getRegInfo();
74 const MachineRegisterInfo &MRI) const {
78 auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
82 const LLT Ty = MRI.getType(Reg);
101 if (isVCC(DstReg, *MRI)) {
104 = TRI.getConstrainedRegClassForOperand(Dst, *MRI);
107 return RBI.constrainGenericRegister(DstReg, *RC, *MRI);
110 if (!isVCC(SrcReg, *MRI)) {
112 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI))
116 = TRI.getConstrainedRegClassForOperand(Src, *MRI);
800 isZero(Register Reg, MachineRegisterInfo &MRI) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp61 MachineRegisterInfo *MRI; member in struct:__anon2385::RISCVMergeBaseOffsetOpt
86 !MRI->hasOneUse(HiLUI.getOperand(0).getReg()))
89 LoADDI = MRI->use_begin(HiLuiDestReg)->getParent();
94 !MRI->hasOneUse(LoADDI->getOperand(0).getReg()))
110 MRI->replaceRegWith(Tail.getOperand(0).getReg(),
143 if (!MRI->hasOneUse(Reg))
146 MachineInstr &OffsetTail = *MRI->getVRegDef(Reg);
155 *MRI->getVRegDef(OffsetTail.getOperand(1).getReg());
159 !MRI->hasOneUse(OffsetLui.getOperand(0).getReg()))
182 assert(MRI
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallLowering.cpp56 MachineRegisterInfo &MRI,
86 ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*PartTy, DL)),
99 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, argument
101 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
111 Register SPReg = MRI.createGenericVirtualRegister(p0);
114 Register OffsetReg = MRI.createGenericVirtualRegister(SType);
117 Register AddrReg = MRI.createGenericVirtualRegister(p0);
136 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
197 MachineRegisterInfo &MRI local
53 splitToValueTypes(const ArgInfo &OrigArg, SmallVectorImpl<ArgInfo> &SplitArgs, const DataLayout &DL, MachineRegisterInfo &MRI, SplitArgTy PerformArgSplit) const argument
230 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, CCAssignFn *AssignFn) argument
302 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, CCAssignFn *AssignFn) argument
313 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, CCAssignFn *AssignFn, MachineInstrBuilder &MIB) argument
338 MachineRegisterInfo &MRI = MF.getRegInfo(); local
382 MachineRegisterInfo &MRI = MF.getRegInfo(); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterBankInfo.cpp274 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
280 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
301 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
337 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
423 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
429 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
445 LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg());
462 const MachineInstr &MI, const MachineRegisterInfo &MRI,
476 return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) ==
481 const MachineRegisterInfo &MRI,
461 hasFPConstraints( const MachineInstr &MI, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const argument
480 onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const argument
494 onlyDefinesFP( const MachineInstr &MI, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const argument
524 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp37 : Builder(B), MRI(Builder.getMF().getRegInfo()), Observer(Observer),
42 void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, argument
44 Observer.changingAllUsesOfReg(MRI, FromReg);
46 if (MRI.constrainRegAttrs(ToReg, FromReg))
47 MRI.replaceRegWith(FromReg, ToReg);
54 void CombinerHelper::replaceRegOpWith(MachineRegisterInfo &MRI, argument
84 LLT DstTy = MRI.getType(DstReg);
85 LLT SrcTy = MRI.getType(SrcReg);
94 const RegisterBank *DstBank = MRI.getRegBankOrNull(DstReg);
95 const RegisterBank *SrcBank = MRI
936 MachineRegisterInfo &MRI = *MIB.getMRI(); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DDisassembler.h64 std::unique_ptr<const llvm::MCRegisterInfo> MRI; member in class:llvm::LLVMDisasmContext
90 std::unique_ptr<const MCRegisterInfo> &&MRI,
98 MAI(std::move(MAI)), MRI(std::move(MRI)), MSI(std::move(MSI)),
112 const MCRegisterInfo *getRegisterInfo() const { return MRI.get(); }
85 LLVMDisasmContext(std::string TripleName, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, const Target *TheTarget, std::unique_ptr<const MCAsmInfo> &&MAI, std::unique_ptr<const MCRegisterInfo> &&MRI, std::unique_ptr<const MCSubtargetInfo> &&MSI, std::unique_ptr<const MCInstrInfo> &&MII, std::unique_ptr<const llvm::MCContext> &&Ctx, std::unique_ptr<const MCDisassembler> &&DisAsm, std::unique_ptr<MCInstPrinter> &&IP) argument

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