Searched refs:Def (Results 76 - 100 of 171) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DMemorySSAUpdater.h101 void insertDef(MemoryDef *Def, bool RenameUses = false);
285 // (MemoryAccess Phi or Def). VMap maps old instructions to cloned
/freebsd-11-stable/contrib/llvm-project/llvm/lib/TableGen/
H A DTGLexer.h49 Bit, Bits, Class, Code, Dag, Def, Foreach, Defm, Field, In, Int, Let, List, enumerator in enum:llvm::tgtok::TokKind
/freebsd-11-stable/contrib/llvm-project/clang/lib/Lex/
H A DPPLexerChange.cpp792 MacroInfo *Def = nullptr;
794 Def = DefMD->getInfo();
801 if (Def || !Macro.getOverriddenMacros().empty())
802 addModuleMacro(LeavingMod, II, Def,
H A DPreprocessor.cpp361 Def = I->second.findDirectiveAtLoc(Loc, SourceMgr); local
362 if (!Def || !Def.getMacroInfo())
364 if (!Def.getMacroInfo()->isObjectLike())
366 if (!MacroDefinitionEquals(Def.getMacroInfo(), Tokens))
368 SourceLocation Location = Def.getLocation();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveIntervals.cpp360 SlotIndex Def = VNI->def; local
361 LR.addSegment(LiveRange::Segment(Def, Def.getDeadSlot(), VNI));
513 SlotIndex Def = VNI->def; local
514 LiveRange::iterator I = LI.FindSegmentContaining(Def);
521 if ((I == LI.begin() || std::prev(I)->end < Def) && !VNI->isPHIDef()) {
522 MachineInstr *MI = getInstructionFromIndex(Def);
527 if (I->end != Def.getDeadSlot())
533 LLVM_DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n");
537 MachineInstr *MI = getInstructionFromIndex(Def);
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H A DRenameIndependentSubregs.cpp323 SlotIndex Def = VNI.def; local
324 MachineBasicBlock &MBB = *Indexes.getMBBFromIndex(Def);
H A DExecutionDomainFix.cpp340 const int Def = RDA->getReachingDef(mi, RC->getRegister(rx));
342 return RDA->getReachingDef(mi, RC->getRegister(I)) <= Def;
H A DMachinePipeliner.cpp2189 MachineInstr *Def = MRI.getVRegDef(Reg); local
2190 while (Def->isPHI()) {
2191 if (!Visited.insert(Def).second)
2193 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2)
2194 if (Def->getOperand(i + 1).getMBB() == BB) {
2195 Def = MRI.getVRegDef(Def->getOperand(i).getReg());
2199 return Def;
2249 MachineInstr *Def = MRI.getVRegDef(BaseOpS->getReg());
2250 if (!Def || !De
2617 isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, MachineInstr *Def, MachineOperand &MO) argument
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H A DSplitKit.h108 /// 3. | o---| Def, live-out.
440 unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def);
/freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/
H A DModuleBuilder.cpp119 if (auto Def = TD->getDefinition())
120 return Def;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.cpp718 int GCNHazardRecognizer::checkVALUHazardsHelper(const MachineOperand &Def, argument
727 if (!TRI->isVGPR(MRI, Def.getReg()))
729 Register Reg = Def.getReg();
751 for (const MachineOperand &Def : VALU->defs()) {
752 WaitStatesNeeded = std::max(WaitStatesNeeded, checkVALUHazardsHelper(Def, MRI));
921 for (const MachineOperand &Def : MI->defs()) {
922 MachineOperand *Op = I->findRegisterUseOperand(Def.getReg(), false, TRI);
H A DSIShrinkInstructions.cpp82 MachineInstr *Def = MRI.getUniqueVRegDef(Reg); local
83 if (Def && Def->isMoveImmediate()) {
84 MachineOperand &MovSrc = Def->getOperand(1);
106 Def->eraseFromParent();
H A DSIInstrInfo.cpp622 for (auto Def = MI, E = MBB.begin(); Def != E; ) {
623 --Def;
624 if (!Def->definesRegister(SrcReg, &RI))
626 if (Def->getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32)
629 MachineOperand &DefOp = Def->getOperand(1);
636 for (auto I = Def; I != MI && SafeToPropagate; ++I)
2440 // If the Def moves immediate and the use is single
2442 MachineInstr *Def = MRI->getUniqueVRegDef(Src0->getReg()); local
2443 if (Def
2460 MachineInstr *Def = MRI->getUniqueVRegDef(Src1->getReg()); local
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H A DSILoadStoreOptimizer.cpp608 // If one of the defs is read, then there is a use of Def between I and the
1663 MachineInstr *Def = MRI->getUniqueVRegDef(Op.getReg());
1664 if (!Def || Def->getOpcode() != AMDGPU::S_MOV_B32 ||
1665 !Def->getOperand(1).isImm())
1668 return Def->getOperand(1).getImm();
1686 MachineInstr *Def = MRI->getUniqueVRegDef(Base.getReg());
1687 if (!Def || Def->getOpcode() != AMDGPU::REG_SEQUENCE
1688 || Def
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp645 Register Def, LHS, RHS; member in struct:Instr
646 Instr(unsigned Opcode, Register Def, Register LHS, Register RHS) argument
647 : Opcode(Opcode), Def(Def), LHS(LHS), RHS(RHS){};
708 Instruction.Opcode, {Instruction.Def}, {Instruction.LHS});
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SpeculationHardening.cpp509 for (auto Def : MI.defs()) {
510 if (Def.isDead())
518 Modified |= makeGPRSpeculationSafe(MBB, NextMBBI, MI, Def.getReg());
/freebsd-11-stable/contrib/llvm-project/clang/include/clang/Lex/
H A DMacroInfo.h385 if (const DefInfo Def = getDefinition())
386 return !Def.isUndefined();
/freebsd-11-stable/contrib/llvm-project/clang/lib/AST/
H A DDeclObjC.cpp96 if (const ObjCProtocolDecl *Def = Proto->getDefinition())
97 if (Def->isHidden() && !AllowHidden)
182 if (const ObjCProtocolDecl *Def = Proto->getDefinition())
183 if (Def->isHidden())
240 if (const ObjCProtocolDecl *Def = Proto->getDefinition())
241 if (Def->isHidden())
1575 if (const ObjCInterfaceDecl *Def = getDefinition()) {
1580 const_cast<ObjCInterfaceDecl*>(Def));
1922 const ObjCProtocolDecl *Def = getDefinition(); local
1923 if (!Def || De
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/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DFixedLenDecoderEmitter.cpp1797 const Record &Def = *CGI.TheDef;
1825 DagInit *Out = Def.getValueAsDag("OutOperandList");
1826 DagInit *In = Def.getValueAsDag("InOperandList");
1851 const std::vector<RecordVal> &Vals = Def.getValues();
1928 LLVM_DEBUG(dbgs() << "Numbered operand mapping for " << Def.getName()
2444 const Record *Def = Inst->TheDef;
2446 if (Def->getValueAsString("Namespace") == "TargetOpcode" ||
2447 Def->getValueAsBit("isPseudo") ||
2448 Def->getValueAsBit("isAsmParserOnly") ||
2449 Def
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/freebsd-11-stable/contrib/llvm-project/clang/lib/Sema/
H A DSemaTemplateInstantiateDecl.cpp1241 EnumDecl *Def = D->getDefinition(); local
1242 if (Def && Def != D) {
1246 if (TypeSourceInfo *TI = Def->getIntegerTypeSourceInfo()) {
1251 SemaRef.CheckEnumRedeclaration(Def->getLocation(), Def->isScoped(),
1263 if (isDeclWithinFunction(D) ? D == Def : Def && !Enum->isScoped()) {
1265 InstantiateEnumDefinition(Enum, Def);
5108 VarDecl *Def local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DSimplifyIndVar.cpp790 /// Add all uses of Def to the current IV's worklist.
792 Instruction *Def, Loop *L,
796 for (User *U : Def->users()) {
801 // If Def is a LoopPhi, it may not be in the Simplified set, so check for
803 if (UI == Def)
815 SimpleIVUsers.push_back(std::make_pair(UI, Def));
791 pushIVUsers( Instruction *Def, Loop *L, SmallPtrSet<Instruction*,16> &Simplified, SmallVectorImpl< std::pair<Instruction*,Instruction*> > &SimpleIVUsers) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DIVDescriptors.cpp958 Value *Def = nullptr;
960 Def = Op1;
962 Def = Op0;
963 return Def;
H A DMemorySSA.cpp450 // If Start is a Def, skip self.
1751 bool Def, Use;
1753 Def = dyn_cast_or_null<MemoryDef>(Template) != nullptr;
1760 assert(Def == DefCheck && (Def || Use == UseCheck) && "Invalid template");
1773 Def = isModSet(ModRef) || isOrdered(I);
1779 if (!Def && !Use)
1783 if (Def)
1909 // If Pred has unreachable predecessors, but has at least a Def, the
1910 // incoming access can be the last Def i
2058 verifyUseInDefs(MemoryAccess *Def, MemoryAccess *Use) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DRDFCopy.cpp92 if (RA.Addr->getKind() == NodeAttrs::Def)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Coroutines/
H A DCoroFrame.cpp290 Value *Def = nullptr; member in class:__anon2548::Spill
295 Spill(Value *Def, llvm::User *U) : Def(Def), User(cast<Instruction>(U)) {} argument
297 Value *def() const { return Def; }
317 // Note that there may be more than one record with the same value of Def in

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