Searched refs:isReg (Results 51 - 75 of 160) sorted by relevance

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/freebsd-10.2-release/contrib/llvm/lib/Target/R600/
H A DR600EmitClauseMarkers.cpp64 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
185 if (!MOI->isReg() || !MOI->isDef() ||
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/
H A DCriticalAntiDepBreaker.cpp171 if (!MO.isReg()) continue;
234 if (!MO.isReg()) continue;
265 if (!MO.isReg()) continue;
335 if (!CheckOper.isReg() || !CheckOper.isDef() ||
578 if (!MO.isReg()) continue;
H A DExecutionDepsFix.cpp509 if (!MO.isReg())
584 if (!mo.isReg()) continue;
593 if (!mo.isReg()) continue;
613 if (!mo.isReg()) continue;
705 if (!mo.isReg()) continue;
H A DMachineSink.cpp311 if (!MO.isReg() || !MO.isUse())
416 if (!MI->getOperand(0).isReg())
424 if (DI->getOperand(0).isReg() &&
502 if (!MO.isReg()) continue; // Ignore non-register operands.
626 if (!MO.isReg()) continue;
H A DTwoAddressInstructionPass.cpp195 if (!MO.isReg())
268 if (!MO.isReg())
438 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
802 if (!MO.isReg())
845 if (!MO.isReg())
988 if (!MO.isReg())
1027 if (!MO.isReg())
1235 if (MO.isReg() &&
1265 if (MOI->isReg())
1381 !MI->getOperand(i).isReg() ||
[all...]
H A DAggressiveAntiDepBreaker.cpp226 if (!MO.isReg() || !MO.isImplicit())
246 if (!MO.isReg()) continue;
348 if (!MO.isReg() || !MO.isDef()) continue;
358 if (!MO.isReg() || !MO.isDef()) continue;
398 if (!MO.isReg() || !MO.isDef()) continue;
441 if (!MO.isReg() || !MO.isUse()) continue;
476 if (!MO.isReg()) continue;
H A DLiveRangeEdit.cpp90 if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
255 if (!MOI->isReg())
308 if (MO.isReg() && TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
H A DPeepholeOptimizer.cpp408 if (!MO.isReg() || !MO.getReg())
439 assert(MODef.isReg() && "Copies must be between registers.");
461 assert(MO.isReg() && "Copies must be between registers.");
546 if (!MO.isReg() || MO.isDef())
H A DSpiller.cpp111 if (!op.isReg() || op.getReg() != li->reg)
H A DMachineVerifier.cpp768 if (!MO.isReg() || !MO.isImplicit())
823 if (!MO->isReg())
833 if (MO->isReg() &&
843 if (!MO->isReg())
849 } else if (MO->isReg() && MO->isTied())
853 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
869 if (!OtherMO.isReg())
1407 if (!MOI->isReg() || !MOI->isDef())
1529 if (!MOI->isReg() || MOI->getReg() != Reg)
H A DPostRASchedulerList.cpp503 if (!MO.isReg()) continue;
522 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
557 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp261 if (!MO.isReg() || MO.isUndef() || MO.isUse())
271 if (!MO.isReg() || MO.isUndef() || MO.isDef())
344 if (!MO.isReg() || MO.isImplicit())
769 if (MO.isReg()) {
840 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
863 if (!MO.isReg() || MO.isUndef() || MO.isUse())
879 if (!MO.isReg() || MO.isUndef() || MO.isDef())
H A DARMAsmPrinter.cpp67 assert(MLoc.isReg() && !Indirect &&
261 if (MI->getOperand(OpNum).isReg()) {
278 if (MI->getOperand(OpNum).isReg()) {
303 if (!MI->getOperand(OpNum).isReg())
324 while (MI->getOperand(RegOps).isReg()) {
366 if (!MO.isReg())
380 if (!MO.isReg())
389 if (!MI->getOperand(OpNum).isReg())
406 if (!MO.isReg())
436 if (!MI->getOperand(OpNum).isReg())
[all...]
H A DARMCodeEmitter.cpp255 if (!MO.isReg()) {
297 if (!MO.isReg()) {
454 if (MO.isReg())
1002 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
1094 if (MO.isReg()) {
1300 if (!MO.isReg() || MO.isImplicit())
1364 if (MO2.isReg()) {
1710 if (Base.isReg()) {
1761 if (!MO.isReg() || MO.isImplicit())
/freebsd-10.2-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp112 MI->getOperand(0).isReg() &&
144 if (MO.isReg()) {
383 unsigned SrcReg2 = (Compare->getOperand(1).isReg() ?
H A DSystemZShortenInst.cpp134 if (MO.isReg()) {
/freebsd-10.2-release/contrib/llvm/include/llvm/CodeGen/
H A DMachineInstr.h644 && getOperand(0).isReg()
852 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
864 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1018 if (MO.isReg() && MO.isTied()) {
/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonFixupHwLoops.cpp167 if (MII->getOperand(1).isReg()) {
/freebsd-10.2-release/contrib/llvm/lib/Target/R600/MCTargetDesc/
H A DR600MCCodeEmitter.cpp172 if (MO.isReg()) {
H A DSIMCCodeEmitter.cpp172 if (MO.isReg())
/freebsd-10.2-release/contrib/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp727 if (MO.isReg()) {
967 if (!MO.isReg()) continue;
979 if (MI.getOperand(0).isReg() &&
985 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
990 if (MI.getOperand(0).isReg() &&
997 if (MO.isReg()) {
1012 if (NumOps > e && MI.getOperand(e).isReg() &&
1018 if (MO.isReg()) {
1027 if (MI.getOperand(0).isReg() &&
1033 if (MO.isReg()
[all...]
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp420 if (MO.isReg()) {
571 if (MCOp1.isImm() && MCOp2.isReg() &&
761 if (!MO.isReg()) {
843 if (!MO.isReg()) {
1014 bool isReg = MO.getReg() != 0; local
1017 if (isReg) {
1023 return Binary | (isAdd << 12) | (isReg << 13);
1069 if (!MO.isReg()) {
1141 if (!MO.isReg()) {
/freebsd-10.2-release/contrib/llvm/utils/TableGen/
H A DFastISelEmitter.cpp94 bool isReg() const { return Repr == OK_Reg; }
102 if (isReg())
285 if (Operands[i].isReg()) {
310 if (Operands[i].isReg()) {
327 if (Operands[i].isReg()) {
/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp468 if (MO.isReg()) {
489 assert(MI.getOperand(OpNo).isReg());
500 assert(MI.getOperand(OpNo).isReg());
/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp432 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
457 if (!MO.isReg())
490 assert(MO.isReg() && "unexpected inline asm memory operand");

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