/freebsd-10.2-release/contrib/llvm/lib/Target/SystemZ/InstPrinter/ |
H A D | SystemZInstPrinter.cpp | 35 O << '%' << getRegisterName(MO.getReg()); 134 printAddress(MI->getOperand(OpNum).getReg(), 140 printAddress(MI->getOperand(OpNum).getReg(), 142 MI->getOperand(OpNum + 2).getReg(), O); 147 unsigned Base = MI->getOperand(OpNum).getReg();
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/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 235 return MI.getOperand(Op).getReg() == ARM::CPSR; 421 unsigned Reg = MO.getReg(); 451 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 572 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { 745 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); 746 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); 880 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 963 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 964 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); [all...] |
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/ |
H A D | CalcSpillWeights.cpp | 48 if (mi->getOperand(0).getReg() == reg) { 50 hreg = mi->getOperand(1).getReg(); 54 hreg = mi->getOperand(0).getReg();
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H A D | MachineRegisterInfo.cpp | 159 if (MO->getReg() != Reg) { 182 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 196 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!"); 201 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!"); 221 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 267 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
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H A D | RegAllocFast.cpp | 222 if (StackSlotForVirtReg[MO.getReg()] != -1) 226 MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(MO.getReg()); 237 if (MO.getReg() == LR.PhysReg) 345 unsigned PhysReg = MO.getReg(); 596 Hint = UseMI.getOperand(0).getReg(); 702 unsigned Reg = MO.getReg(); 718 unsigned Reg = MO.getReg(); 732 unsigned Reg = MO.getReg(); 757 unsigned Reg = MO.getReg(); 773 unsigned Reg = MO.getReg(); [all...] |
H A D | RegisterScavenging.cpp | 132 unsigned Reg = MO.getReg(); 204 unsigned Reg = MO.getReg(); 311 if (!MO.isReg() || MO.isUndef() || !MO.getReg()) 313 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 320 for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI) 371 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) && 372 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) 373 Candidates.reset(MO.getReg());
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H A D | MachineCSE.cpp | 121 unsigned Reg = MO.getReg(); 131 unsigned SrcReg = DefMI->getOperand(1).getReg(); 169 if (!MO.isReg() || !MO.getReg()) 171 if (!TRI->regsOverlap(MO.getReg(), Reg)) 203 unsigned Reg = MO.getReg(); 222 unsigned Reg = MO.getReg(); 298 unsigned MOReg = MO.getReg(); 384 TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 521 unsigned OldReg = MO.getReg(); 522 unsigned NewReg = CSMI->getOperand(i).getReg(); [all...] |
/freebsd-10.2-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | LiveRangeEdit.h | 133 unsigned getReg() const { return getParent().reg; } function in class:llvm::LiveRangeEdit 156 return createEmptyIntervalFrom(getReg()); 160 return createFrom(getReg());
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/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.h | 64 unsigned RegNo = MO.getReg(); 86 O << getRegisterName(MO1.getReg()) 96 O << getRegisterName(MO1.getReg())
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H A D | HexagonExpandPredSpillCode.cpp | 88 unsigned FP = MI->getOperand(0).getReg(); 93 int SrcReg = MI->getOperand(2).getReg(); 132 int DstReg = MI->getOperand(0).getReg(); 135 unsigned FP = MI->getOperand(1).getReg();
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/freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/InstPrinter/ |
H A D | PPCInstPrinter.cpp | 65 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { 255 unsigned CCReg = MI->getOperand(OpNo).getReg(); 275 if (MI->getOperand(OpNo+1).getReg() == PPC::R0) 287 if (MI->getOperand(OpNo).getReg() == PPC::R0) 324 const char *RegName = getRegisterName(Op.getReg());
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/freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 240 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); 241 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); 253 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); 254 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
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/freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCCodeEmitter.cpp | 147 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); 148 return 0x80 >> TM.getRegisterInfo()->getEncodingValue(MO.getReg()); 281 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); 282 return TM.getRegisterInfo()->getEncodingValue(MO.getReg());
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/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMMCInstLower.cpp | 72 if (MO.isImplicit() && MO.getReg() != ARM::CPSR) 75 MCOp = MCOperand::CreateReg(MO.getReg());
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H A D | ARMBaseInstrInfo.cpp | 158 unsigned WBReg = WB.getReg(); 159 unsigned BaseReg = Base.getReg(); 160 unsigned OffReg = Offset.getReg(); 213 get(MemOpc), MI->getOperand(0).getReg()) 217 get(MemOpc)).addReg(MI->getOperand(1).getReg()) 224 get(MemOpc), MI->getOperand(0).getReg()) 228 get(MemOpc)).addReg(MI->getOperand(1).getReg()) 240 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 241 unsigned Reg = MO.getReg(); 416 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); [all...] |
H A D | Thumb2ITBlockPass.cpp | 66 unsigned Reg = MO.getReg(); 118 unsigned DstReg = MI->getOperand(0).getReg(); 119 unsigned SrcReg = MI->getOperand(1).getReg(); 143 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
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/freebsd-10.2-release/contrib/llvm/lib/Target/R600/ |
H A D | R600OptimizeVectorRegisters.cpp | 70 if (isImplicitlyDef(MRI, MO.getReg())) 73 RegToChan[MO.getReg()] = Chan; 179 unsigned Reg = RSI->Instr->getOperand(0).getReg(); 184 unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg(); 279 if (PreviousRegSeqByReg[MOp->getReg()].empty()) 281 std::vector<MachineInstr *> MIs = PreviousRegSeqByReg[MOp->getReg()]; 330 unsigned Reg = MI->getOperand(1).getReg(); 343 unsigned Reg = MI->getOperand(0).getReg();
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H A D | R600Packetizer.cpp | 65 return TRI.getHWRegChan(MI->getOperand(0).getReg()); 95 unsigned Dst = BI->getOperand(DstIdx).getReg(); 141 unsigned Src = MI->getOperand(OperandIdx).getReg(); 192 unsigned PredI = (OpI > -1)?MII->getOperand(OpI).getReg():0, 193 PredJ = (OpJ > -1)?MIJ->getOperand(OpJ).getReg():0; 204 if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
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/freebsd-10.2-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64FrameLowering.cpp | 115 && MBBI->getOperand(0).getReg() == AArch64::X29) { 186 unsigned Reg = MRI->getDwarfRegNum(I->getReg(), true); 230 MIB.addReg(JumpTarget.getReg(), RegState::Kill); 446 unsigned Reg = CSI[i].getReg(); 463 if (i + 1 < CSI.size() && TheClass.contains(CSI[i+1].getReg())) { 469 StLow = getKillRegState(determinePrologueDeath(MBB, CSI[i+1].getReg())); 470 StHigh = getKillRegState(determinePrologueDeath(MBB, CSI[i].getReg())); 477 .addReg(CSI[i+1].getReg(), StLow) 478 .addReg(CSI[i].getReg(), StHigh); 485 State = getKillRegState(determinePrologueDeath(MBB, CSI[i].getReg())); [all...] |
/freebsd-10.2-release/contrib/llvm/lib/MC/ |
H A D | MCInst.cpp | 23 OS << "Reg:" << getReg();
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/freebsd-10.2-release/contrib/llvm/include/llvm/MC/ |
H A D | MachineLocation.h | 54 unsigned getReg() const { return Register; } function
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/freebsd-10.2-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.cpp | 82 SrcReg = src.getReg(); 83 DestReg = dest.getReg(); 263 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()) 269 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
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/freebsd-10.2-release/contrib/llvm/lib/Target/XCore/InstPrinter/ |
H A D | XCoreInstPrinter.cpp | 75 printRegName(O, Op.getReg());
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/freebsd-10.2-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreAsmPrinter.cpp | 210 O << XCoreInstPrinter::getRegisterName(MO.getReg()); 265 << XCoreInstPrinter::getRegisterName(MI->getOperand(0).getReg()) << ", " 266 << XCoreInstPrinter::getRegisterName(MI->getOperand(1).getReg()); 274 << XCoreInstPrinter::getRegisterName(MI->getOperand(1).getReg()) << '\n';
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/freebsd-10.2-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZElimCompare.cpp | 114 MI->getOperand(0).getReg() == Reg && 131 if (MI->getOperand(1).getReg() == Reg && 145 if (unsigned MOReg = MO.getReg()) { 192 unsigned SrcReg = Compare->getOperand(0).getReg(); 329 unsigned SrcReg = Compare->getOperand(0).getReg(); 382 unsigned SrcReg = Compare->getOperand(0).getReg(); 384 Compare->getOperand(1).getReg() : 0);
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