Searched refs:CPU (Results 151 - 169 of 169) sorted by relevance

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/freebsd-10.2-release/contrib/llvm/tools/clang/lib/Frontend/
H A DFrontendActions.cpp357 Out.indent(4) << " CPU: " << TargetOpts.CPU << "\n";
H A DCompilerInvocation.cpp1617 Opts.CPU = Args.getLastArgValue(OPT_target_cpu);
1762 code = hash_combine(code, TargetOpts->Triple, TargetOpts->CPU,
/freebsd-10.2-release/contrib/llvm/tools/clang/lib/CodeGen/
H A DBackendUtil.cpp487 TargetMachine *TM = TheTarget->createTargetMachine(Triple, TargetOpts.CPU,
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAsmBackend.cpp665 StringRef TT, StringRef CPU) {
663 createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
/freebsd-10.2-release/crypto/openssl/crypto/
H A Dsparccpuid.S44 ! to determine if the CPU the code is executing on is V8- or
/freebsd-10.2-release/sys/dev/pms/RefTisa/sat/src/
H A Dsmdefs.h575 * CPU buffer access macro *
660 #error (Host CPU endianess undefined!!)
/freebsd-10.2-release/sys/cddl/contrib/opensolaris/uts/intel/dtrace/
H A Dfasttrap_isa.c755 pid_mtx = &cpu_core[CPU->cpu_id].cpuc_pid_lock;
1053 pid_mtx = &cpu_core[CPU->cpu_id].cpuc_pid_lock;
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp586 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU, argument
588 if (CPU == "xscale")
/freebsd-10.2-release/sys/dev/pms/RefTisa/tisa/sassata/common/
H A Dtddefs.h850 * CPU buffer access macro *
935 #error (Host CPU endianess undefined!!)
/freebsd-10.2-release/sys/cddl/contrib/opensolaris/uts/common/dtrace/
H A Ddtrace.c313 #define curcpu CPU->cpu_id
430 uint_t actv = CPU->cpu_intr_actv >> (LOCK_LEVEL + 1); \
641 * Most counters stored to in probe context are per-CPU counters.
643 * arcane that they don't merit per-CPU storage. If these counters
1587 * this CPU was selected to accept another CPU's
1599 * situation where a CPU has done deallocations (we
1603 * CPU, yet we also don't want to allow this condition
1607 * drops). To deal with this, we look for some CPU
1609 * rinsing list -- and then we borrow this CPU t
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H A Dfasttrap.c1128 cpu_t *cur, *cpu = CPU;
/freebsd-10.2-release/sys/mips/mips/
H A Dexception.S103 * which the CPU jumps in response to an exception or a TLB miss.
268 * Save CPU and CP0 register state.
384 * Save CPU state, building 'frame'.
396 * Update interrupt and CPU mask in saved status register
641 * Save CPU state, building 'frame'.
653 * Update interrupt and CPU mask in saved status register
1125 PTR_ADDU a0, a0, U_PCB_REGS # first arg is ptr to CPU registers
/freebsd-10.2-release/contrib/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp1003 const ConstantInt *CPU = cast<ConstantInt>(I.getOperand());
1004 unsigned Index = unsigned(CPU->getZExtValue());
/freebsd-10.2-release/contrib/binutils/gas/config/
H A Dtc-mips.c206 -mipsN command line option, and the default CPU. */
220 -nomips16 command line options, and the default CPU. */
248 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
249 command line option, and the default CPU. */
436 /* Return true if the given CPU supports the MIPS16 ASE. */
441 /* True if CPU has a dror instruction. */
442 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
444 /* True if CPU ha
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/freebsd-10.2-release/sys/dev/pms/RefTisa/sallsdk/api/
H A Dsa.h119 #error (Host CPU endianess undefined!!)
615 #if defined(SA_CPU_LITTLE_ENDIAN) /* CPU little endain */
2086 bit32 tickCount0; /* tick count in second for internal CPU-0 */
2087 bit32 tickCount1; /* tick count in second for internal CPU-1 */
2088 bit32 tickCount2; /* tick count in second for internal CPU-2 */
/freebsd-10.2-release/contrib/bmake/
H A Dconfigure5385 also use the system CPU time. And page faults (I/O) for Linux. */
5393 sleep(1); /* Give up the CPU. */
/freebsd-10.2-release/contrib/llvm/tools/clang/lib/Serialization/
H A DASTReader.cpp141 CHECK_TARGET_OPT(CPU, "target CPU");
4005 TargetOpts.CPU = ReadString(Record, Idx);
H A DASTWriter.cpp1098 AddString(TargetOpts.CPU, Record);
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp8037 StringRef CPU = getParser().parseStringToEndOfStatement().trim(); local
8038 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);

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