/freebsd-10.1-release/contrib/llvm/tools/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
H A D | BasicValueFactory.h | 185 const llvm::APSInt& V2); 191 getPersistentSValPair(const SVal& V1, const SVal& V2);
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/freebsd-10.1-release/sbin/mount_nfs/ |
H A D | mount_nfs.c | 120 V2, enumerator in enum:mountmode 173 mountmode = V2; 269 mountmode = V2; 320 mountmode = V2; 939 } else if (trymntmode == V2) { 960 trymntmode = V2; 1003 trymntmode = V2; 1058 trymntmode = V2;
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/freebsd-10.1-release/contrib/libreadline/examples/rlfe/ |
H A D | rlfe.c | 139 #define DPRINT2(FMT, V1, V2) (fprintf(logfile, FMT, V1, V2), fflush(logfile)) 143 #define DPRINT2(FMT, V1, V2) ((void) 0) /* Do nothing */
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/freebsd-10.1-release/contrib/llvm/tools/clang/lib/Driver/ |
H A D | ToolChains.h | 293 bool isIPhoneOSVersionLT(unsigned V0, unsigned V1=0, unsigned V2=0) const { 295 return TargetVersion < VersionTuple(V0, V1, V2); 298 bool isMacosxVersionLT(unsigned V0, unsigned V1=0, unsigned V2=0) const { 300 return TargetVersion < VersionTuple(V0, V1, V2);
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/freebsd-10.1-release/contrib/llvm/include/llvm/Support/ |
H A D | ConstantFolder.h | 220 Constant *CreateShuffleVector(Constant *V1, Constant *V2, argument 222 return ConstantExpr::getShuffleVector(V1, V2, Mask);
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H A D | TargetFolder.h | 244 Constant *CreateShuffleVector(Constant *V1, Constant *V2, argument 246 return Fold(ConstantExpr::getShuffleVector(V1, V2, Mask));
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H A D | NoFolder.h | 280 Instruction *CreateShuffleVector(Constant *V1, Constant *V2, argument 282 return new ShuffleVectorInst(V1, V2, Mask);
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/freebsd-10.1-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonRegisterInfo.cpp | 61 case HexagonSubtarget::V2: 108 case HexagonSubtarget::V2:
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/freebsd-10.1-release/contrib/llvm/tools/clang/lib/Headers/ |
H A D | avx2intrin.h | 160 #define _mm256_blend_epi16(V1, V2, M) __extension__ ({ \ 162 __m256i __V2 = (V2); \ 761 #define _mm_blend_epi32(V1, V2, M) __extension__ ({ \ 763 __m128i __V2 = (V2); \ 766 #define _mm256_blend_epi32(V1, V2, M) __extension__ ({ \ 768 __m256i __V2 = (V2); \ 844 #define _mm256_permute2x128_si256(V1, V2, M) __extension__ ({ \ 846 __m256i __V2 = (V2); \ 853 #define _mm256_inserti128_si256(V1, V2, O) __extension__ ({ \ 855 __m128i __V2 = (V2); \ [all...] |
/freebsd-10.1-release/contrib/llvm/lib/CodeGen/ |
H A D | MachineModuleInfo.cpp | 49 virtual void allUsesReplacedWith(Value *V2); 246 void MMIAddrLabelMapCallbackPtr::allUsesReplacedWith(Value *V2) { argument 247 Map->UpdateForRAUWBlock(cast<BasicBlock>(getValPtr()), cast<BasicBlock>(V2));
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/freebsd-10.1-release/contrib/llvm/lib/Transforms/Instrumentation/ |
H A D | MemorySanitizer.cpp | 1176 // S = (S1 & S2) | (V1 & S2) | (S1 & V2) 1180 Value *V2 = I.getOperand(1); local 1183 V2 = IRB.CreateIntCast(V2, S2->getType(), false); 1187 Value *S1V2 = IRB.CreateAnd(S1, V2); 1198 // S = (S1 & S2) | (~V1 & S2) | (S1 & ~V2) 1202 Value *V2 = IRB.CreateNot(I.getOperand(1)); local 1205 V2 = IRB.CreateIntCast(V2, S2->getType(), false); 1209 Value *S1V2 = IRB.CreateAnd(S1, V2); 1322 Value *V2 = local 1534 Value *V2 = I.getOperand(1); local [all...] |
H A D | DataFlowSanitizer.cpp | 182 Value *combineShadows(Value *V1, Value *V2, Instruction *Pos); 813 Value *DataFlowSanitizer::combineShadows(Value *V1, Value *V2, argument 816 return V2; 817 if (V2 == ZeroShadow) 819 if (V1 == V2) 823 Value *Ne = IRB.CreateICmpNE(V1, V2); 829 CallInst *Call = ThenIRB.CreateCall2(DFSanUnionFn, V1, V2);
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/freebsd-10.1-release/contrib/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 60 SDValue V2); 165 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, argument 169 return Insert128BitVector(V, V2, NumElems/2, DAG, dl); 172 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT, argument 176 return Insert256BitVector(V, V2, NumElems/2, DAG, dl); 3315 SDValue V1, SDValue V2, unsigned TargetMask, 3322 return DAG.getNode(Opc, dl, VT, V1, V2, 3328 SDValue V1, SDValue V2, SelectionDAG &DAG) { 3340 return DAG.getNode(Opc, dl, VT, V1, V2); 4102 /// the second half of V2 3314 getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) argument 3327 getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG) argument 4646 ShouldXformToMOVLP(SDNode *V1, SDNode *V2, ArrayRef<int> Mask, MVT VT) argument 4689 SDValue V2 = N->getOperand(1); local 4793 getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1, SDValue V2) argument 4804 getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1, SDValue V2) argument 4816 getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1, SDValue V2) argument 4917 getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, bool IsZero, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument 6019 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, local 6155 SDValue V2 = Op.getOperand(1); local 6176 SDValue V2 = SVOp->getOperand(1); local 6241 SDValue V2 = SVOp->getOperand(1); local 6496 SDValue V2 = SVOp->getOperand(1); local 6625 SDValue V2 = SVOp->getOperand(1); local 6702 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1)); local 6860 SDValue V2 = SVOp->getOperand(1); local 7209 SDValue V2 = Op.getOperand(1); local 7264 SDValue V2 = Op.getOperand(1); local 12985 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl); local 16162 SDValue V2 = SVOp->getOperand(1); local 17637 SDValue V2 = N->getOperand(1); local [all...] |
/freebsd-10.1-release/contrib/llvm/include/llvm/ADT/ |
H A D | APInt.h | 1684 inline bool operator==(uint64_t V1, const APInt &V2) { return V2 == V1; } 1686 inline bool operator!=(uint64_t V1, const APInt &V2) { return V2 != V1; }
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/freebsd-10.1-release/contrib/llvm/lib/Target/NVPTX/InstPrinter/ |
H A D | NVPTXInstPrinter.cpp | 256 if (Imm == NVPTX::PTXLdStInstCode::V2)
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/freebsd-10.1-release/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/ |
H A D | ExprEngineC.cpp | 900 DefinedSVal V2 = V2_untested.castAs<DefinedSVal>(); local 917 SVal Result = evalBinOp(state, Op, V2, RHS, U->getType()); 930 svalBuilder.evalEQ(state, V2,svalBuilder.makeZeroVal(U->getType())); 950 state = state->BindExpr(U, LCtx, U->isPostfix() ? V2 : Result);
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/freebsd-10.1-release/sys/geom/raid/ |
H A D | md_ddf.h | 269 uint8_t V2[16]; member in struct:ddf_vdc_record
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/freebsd-10.1-release/contrib/llvm/lib/Transforms/Scalar/ |
H A D | Reassociate.cpp | 991 Value *V2 = EmitAddTreeOfValues(I, Ops); local 992 return BinaryOperator::CreateAdd(V2, V1, "tmp", I); 1531 Instruction *V2 = BinaryOperator::CreateMul(V, MaxOccVal, "tmp", I); 1535 RedoInsts.insert(V2); 1540 return V2; 1545 Ops.insert(Ops.begin(), ValueEntry(getRank(V2), V2));
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/freebsd-10.1-release/contrib/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineAndOrXor.cpp | 1999 Value *V1 = 0, *V2 = 0; local 2008 match(A, m_Add(m_Value(V1), m_Value(V2)))) { 2010 if (V1 == B && MaskedValueIsZero(V2, C2->getValue())) 2012 if (V2 == B && MaskedValueIsZero(V1, C2->getValue())) 2017 match(B, m_Add(m_Value(V1), m_Value(V2)))) { 2019 if (V1 == A && MaskedValueIsZero(V2, C1->getValue())) 2021 if (V2 == A && MaskedValueIsZero(V1, C1->getValue())) 2029 if (match(A, m_Or(m_Value(V1), m_Value(V2))) && 2030 ((V1 == B && MaskedValueIsZero(V2, ~C1->getValue())) || // (V|N) 2031 (V2 [all...] |
H A D | InstCombineLoadStoreAlloca.cpp | 419 // load (select (Cond, &V1, &V2)) --> select(Cond, load &V1, load &V2). 425 LoadInst *V2 = Builder->CreateLoad(SI->getOperand(2), local 428 V2->setAlignment(Align); 429 return SelectInst::Create(SI->getCondition(), V1, V2);
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H A D | InstCombineShifts.cpp | 406 Value *V1, *V2; local 464 m_And(m_OneUse(m_Shr(m_Value(V1), m_Value(V2))), 465 m_ConstantInt(CC))) && V2 == Op1) {
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/freebsd-10.1-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 271 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); 272 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); 273 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); 1613 SDValue V2, SDValue V3) { 1622 V2, SubReg2, V3, SubReg3 }; 1628 SDValue V2, SDValue V3) { 1636 V2, SubReg2, V3, SubReg3 }; 1642 SDValue V2, SDValue V3) { 1650 V2, SubReg2, V3, SubReg3 }; 1971 SDValue V2 local 1612 createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument 1627 createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument 1641 createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument 2021 SDValue V2 = N->getOperand(Vec0Idx + 2); local 2139 SDValue V2 = N->getOperand(Vec0Idx + 2); local 2272 SDValue V2 = N->getOperand(FirstTblReg + 2); local [all...] |
/freebsd-10.1-release/contrib/llvm/lib/IR/ |
H A D | Verifier.cpp | 366 const Value *V1 = 0, const Value *V2 = 0, 370 WriteValue(V2); 407 #define Assert2(C, M, V1, V2) \ 408 do { if (!(C)) { CheckFailed(M, V1, V2); return; } } while (0) 409 #define Assert3(C, M, V1, V2, V3) \ 410 do { if (!(C)) { CheckFailed(M, V1, V2, V3); return; } } while (0) 411 #define Assert4(C, M, V1, V2, V3, V4) \ 412 do { if (!(C)) { CheckFailed(M, V1, V2, V3, V4); return; } } while (0)
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/freebsd-10.1-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 983 const Value *V2 = Store->getSrcValue(); local 984 if (!V1 || !V2) 991 if (V1 == V2 && End1 == End2) 995 AliasAnalysis::Location(V2, End2, Store->getTBAAInfo()));
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/freebsd-10.1-release/contrib/llvm/lib/Transforms/Utils/ |
H A D | SimplifyCFG.cpp | 525 std::vector<ValueEqualityComparisonCase> *V1 = &C1, *V2 = &C2; local 527 // Make V1 be smaller than V2. 528 if (V1->size() > V2->size()) 529 std::swap(V1, V2); 533 // Just scan V2. 535 for (unsigned i = 0, e = V2->size(); i != e; ++i) 536 if (TheVal == (*V2)[i].Value) 542 array_pod_sort(V2->begin(), V2->end()); 543 unsigned i1 = 0, i2 = 0, e1 = V1->size(), e2 = V2 [all...] |