/freebsd-10.1-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | DFAPacketizer.h | 96 const TargetInstrInfo *TII; member in class:llvm::VLIWPacketizerList
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H A D | ResourcePriorityQueue.h | 62 const TargetInstrInfo *TII; member in class:llvm::ResourcePriorityQueue
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H A D | RegisterScavenging.h | 33 const TargetInstrInfo *TII; member in class:llvm::RegScavenger
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H A D | VirtRegMap.h | 42 const TargetInstrInfo *TII; member in class:llvm::VirtRegMap
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/freebsd-10.1-release/contrib/llvm/lib/CodeGen/ |
H A D | AggressiveAntiDepBreaker.h | 120 const TargetInstrInfo *TII; member in class:llvm::AggressiveAntiDepBreaker
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H A D | VirtRegMap.cpp | 55 TII = mf.getTarget().getInstrInfo(); 158 const TargetInstrInfo *TII; member in class:__anon2329::VirtRegRewriter 206 TII = TM->getInstrInfo(); 370 MI->setDesc(TII->get(TargetOpcode::KILL));
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H A D | InlineSpiller.cpp | 67 const TargetInstrInfo &TII; member in class:__anon2246::InlineSpiller 152 TII(*mf.getTarget().getInstrInfo()), 251 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) 255 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) 605 if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) { 727 TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot, 784 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) { 787 MI->setDesc(TII.get(TargetOpcode::KILL)); 983 unsigned InstrReg = TII.isLoadFromStackSlot(MI, FI); 986 InstrReg = TII [all...] |
H A D | StackSlotColoring.cpp | 50 const TargetInstrInfo *TII; member in class:__anon2323::StackSlotColoring 381 if (TII->isStackSlotCopy(I, FirstSS, SecondSS) && 395 if (!(LoadReg = TII->isLoadFromStackSlot(I, FirstSS))) continue; 396 if (!(StoreReg = TII->isStoreToStackSlot(NextMI, SecondSS))) continue; 426 TII = MF.getTarget().getInstrInfo();
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H A D | MachineLICM.cpp | 64 const TargetInstrInfo *TII; member in class:__anon2262::MachineLICM 324 TII = TM->getInstrInfo(); 484 (TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI))) 806 if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond, false) && Cond.empty()) 897 if (!I.isSafeToMove(TII, AA, DontMoveAcrossStore)) 1029 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i)) 1059 if (!TII->hasLowDefLatency(InstrItins, &MI, i)) 1171 if (TII->isTriviallyReMaterializable(&MI, AA)) 1233 if (!TII->isTriviallyReMaterializable(&MI, AA) && 1256 TII [all...] |
H A D | CriticalAntiDepBreaker.cpp | 33 TII(MF.getTarget().getInstrInfo()), 165 TII->isPredicated(MI); 177 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF); 218 if (!TII->isPredicated(MI)) { 272 NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF); 567 TII->isPredicated(MI))
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H A D | MachineCopyPropagation.cpp | 36 const TargetInstrInfo *TII; member in class:__anon2258::MachineCopyPropagation 136 MI->setDesc(TII->get(TargetOpcode::KILL)); 326 TII = MF.getTarget().getInstrInfo();
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H A D | BranchFolding.h | 90 const TargetInstrInfo *TII; member in class:llvm::BranchFolder
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H A D | LiveDebugVariables.cpp | 130 LiveIntervals &LIS, const TargetInstrInfo &TII); 929 const TargetInstrInfo &TII) { 935 BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE), 938 BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE)) 943 const TargetInstrInfo &TII) { 955 insertDebugValue(MBB, Start, LocNo, LIS, TII); 965 insertDebugValue(MBB, Start, LocNo, LIS, TII); 977 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); local 981 userValues[i]->emitDebugValues(VRM, *LIS, *TII); 926 insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx, unsigned LocNo, LiveIntervals &LIS, const TargetInstrInfo &TII) argument 942 emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS, const TargetInstrInfo &TII) argument
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H A D | MachineBlockPlacement.cpp | 177 const TargetInstrInfo *TII; member in class:__anon2254::MachineBlockPlacement 891 if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond) || !FI->canFallThrough()) 993 if (!TII->AnalyzeBranch(*PrevBB, TBB, FBB, Cond)) { 1010 if (TII->AnalyzeBranch(*PrevBB, TBB, FBB, Cond)) { 1020 !TII->ReverseBranchCondition(Cond)) { 1026 TII->RemoveBranch(*PrevBB); 1027 TII->InsertBranch(*PrevBB, FBB, TBB, Cond, dl); 1038 if (!TII->AnalyzeBranch(F.back(), TBB, FBB, Cond)) 1112 TII = F.getTarget().getInstrInfo();
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H A D | MachineRegisterInfo.cpp | 70 const TargetInstrInfo *TII = TM.getInstrInfo(); local 83 I->getRegClassConstraint(I.getOperandNo(), TII, 373 const TargetInstrInfo &TII) { 388 TII.get(TargetOpcode::COPY), LiveIns[i].second) 371 EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII) argument
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H A D | PrologEpilogInserter.cpp | 177 const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); local 185 int FrameSetupOpcode = TII.getCallFrameSetupOpcode(); 186 int FrameDestroyOpcode = TII.getCallFrameDestroyOpcode(); 324 const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); local 340 TII.storeRegToStackSlot(*EntryBlock, I, Reg, true, CSI[i].getFrameIdx(), 368 TII.loadRegFromStackSlot(*MBB, I, Reg, CSI[i].getFrameIdx(), RC, TRI); 689 const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); local 694 int FrameSetupOpcode = TII.getCallFrameSetupOpcode(); 695 int FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
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/freebsd-10.1-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 764 const TargetInstrInfo &TII, 773 MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ)) 883 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 939 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 943 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 944 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 947 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 951 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 952 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 970 const TargetInstrInfo *TII local 762 expandPseudoDIV(MachineInstr *MI, MachineBasicBlock &MBB, const TargetInstrInfo &TII, bool Is64Bit) argument 1126 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 1208 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local [all...] |
H A D | MipsSEISelLowering.cpp | 2615 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 2640 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB); 2644 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) 2646 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 2650 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) 2654 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 2680 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 2705 BuildMI(BB, DL, TII->get(BranchOp)) 2711 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1) 2713 BuildMI(*FBB, FBB->end(), DL, TII 2741 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 2775 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 2804 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 2837 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 2869 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 2900 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 2928 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 2957 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local [all...] |
H A D | MipsSEISelDAGToDAG.cpp | 131 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 152 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) 154 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) 156 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1) 166 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) 168 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) 181 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) 183 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); 184 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1) 210 BuildMI(MBB, I, DL, TII [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/ARM/ |
H A D | Thumb2ITBlockPass.cpp | 32 const Thumb2InstrInfo *TII; member in class:__anon2475::Thumb2ITBlockPass 182 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT)) 257 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
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H A D | ARMLoadStoreOptimizer.cpp | 65 const TargetInstrInfo *TII; member in struct:__anon2451::ARMLoadStoreOpt 128 const TargetInstrInfo *TII, 342 BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase) 353 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode)) 857 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) 927 const TargetInstrInfo *TII, 1010 BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) 1021 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) 1026 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) 1033 BuildMI(MBB, MBBI, dl, TII 925 MergeBaseUpdateLoadStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const TargetInstrInfo *TII, bool &Advance, MachineBasicBlock::iterator &I) argument 1152 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument 1547 const TargetInstrInfo *TII; member in struct:__anon2452::ARMPreAllocLoadStoreOpt [all...] |
H A D | ARMBaseInstrInfo.h | 401 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 407 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 411 int NumBytes, const TargetInstrInfo &TII, 429 const ARMBaseInstrInfo &TII); 433 const ARMBaseInstrInfo &TII);
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H A D | ARMISelLowering.cpp | 1201 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 1202 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); 1915 const TargetInstrInfo *TII) { 1926 if (!TII->isLoadFromStackSlot(Def, FI)) 2064 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 2091 MFI, MRI, TII)) 6218 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 6265 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 6269 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 6271 BuildMI(BB, dl, TII 1913 MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII) argument 6305 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 6400 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 6518 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 6700 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 6747 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 6862 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 7313 emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos, const TargetInstrInfo *TII, DebugLoc dl, unsigned LdSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2) argument 7345 emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos, const TargetInstrInfo *TII, DebugLoc dl, unsigned StSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2) argument 7379 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 7613 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); local 8008 const ARMBaseInstrInfo *TII = local [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/X86/ |
H A D | X86VZeroUpper.cpp | 44 const TargetInstrInfo *TII; // Machine instruction info. member in struct:__anon2676::VZeroUpperInserter 173 TII = MF.getTarget().getInstrInfo(); 297 BuildMI(BB, I, dl, TII->get(X86::VZEROUPPER));
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H A D | X86FloatingPoint.cpp | 75 const TargetInstrInfo *TII; // Machine instruction info. member in struct:__anon2659::FPS 253 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); 262 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); 356 TII = MF.getTarget().getInstrInfo(); 841 I->setDesc(TII->get(Opcode)); 845 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); 876 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr)).addReg(STReg); 931 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0)); 976 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 1024 MI->setDesc(TII [all...] |