/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 1532 // add (sext i1), X -> sub X, (zext i1) 1534 N0.getOperand(0).getValueType() == MVT::i1 && 1535 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 3440 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 4102 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4106 (VT0 == MVT::i1 || 4123 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4129 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4135 if (VT == MVT::i1 [all...] |
H A D | SelectionDAGBuilder.cpp | 305 // Handle cases such as i8 -> <1 x i1> 725 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 727 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 1613 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1625 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1630 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1986 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 5123 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 5490 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
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H A D | LegalizeDAG.cpp | 760 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 925 // Some targets pretend to have an i1 loading operation, and actually 931 // Until such a way is found, don't insist on promoting i1 here. 932 (SrcVT != MVT::i1 || 933 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 3608 // We test only the i1 bit. Skip the AND if UNDEF.
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H A D | SelectionDAG.cpp | 2929 // Always fold shifts of i1 values so the code generator doesn't need to 2932 if (VT == MVT::i1) 4739 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
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/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 630 // ARM does not have i1 sign extending load. 631 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 637 setIndexedLoadAction(im, MVT::i1, Legal); 641 setIndexedStoreAction(im, MVT::i1, Legal); 775 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 7616 // Detects these expressions where cc is an i1 value: 7657 if (CC.getValueType() != MVT::i1) 7685 // Also recognize sext/zext from i1: 9534 DAG.getValueType(MVT::i1)); 9695 case MVT::i1 [all...] |
H A D | ARMISelDAGToDAG.cpp | 1443 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) { 1510 case MVT::i1:
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/freebsd-10.0-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1250 // Sparc doesn't have i1 sign extending load 1251 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 1263 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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/freebsd-10.0-release/tools/tools/net80211/wesside/wesside/ |
H A D | wesside.c | 1655 unsigned char* m1, unsigned char* i1, 1663 inet_aton(i1, &sip); 1654 do_arp(unsigned char* buf, unsigned short op, unsigned char* m1, unsigned char* i1, unsigned char* m2, unsigned char* i2) argument
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/freebsd-10.0-release/contrib/binutils/bfd/ |
H A D | elfxx-ia64.c | 854 bfd_vma t0, t1, i0, i1, i2; 864 i1 = 0x4000000000LL; 874 t0 = (i1 << 46) | (i0 << 5) | template; 875 t1 = (i2 << 23) | (i1 >> 18); 852 bfd_vma t0, t1, i0, i1, i2; local
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H A D | elf32-arm.c | 5050 bfd_vma i1 = j1 ^ s ? 0 : 1; local 5053 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
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/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 68 // AArch64 does not have i1 loads, or much of anything for i1 really. 69 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 70 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 71 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 265 // promotion from i1 for scalar types. Otherwise LegalizeTypes can get itself
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/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 92 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 93 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 99 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 104 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 241 // We cannot sextinreg(i1). Expand to shifts. 242 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 284 setOperationAction(ISD::VAARG, MVT::i1, Promote); 285 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
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/freebsd-10.0-release/contrib/ncurses/include/ |
H A D | Caps.uwin | 340 init_1string is1 str i1 - - YB-G- initialization string
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H A D | Caps | 372 init_1string is1 str i1 - - YB-G- initialization string
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H A D | Caps.aix4 | 372 init_1string is1 str i1 - - YB-G- initialization string
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H A D | Caps.hpux11 | 374 init_1string is1 str i1 - - YB-G- initialization string
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H A D | Caps.keys | 374 init_1string is1 str i1 - - YB-G- initialization string
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/freebsd-10.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 255 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 275 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 291 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 293 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 316 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 318 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 332 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 409 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 472 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 1748 if (Subtarget->is64Bit() && VT == MVT::i1 [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 575 if (VT == MVT::i1) {
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/freebsd-10.0-release/crypto/openssl/crypto/bn/asm/ |
H A D | sparcv8.S | 536 #define ap(I) [%i1+4*I]
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H A D | sparcv8plus.S | 643 #define ap(I) [%i1+4*I]
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/freebsd-10.0-release/contrib/gcc/ |
H A D | fold-const.c | 1814 tree i1 = TREE_IMAGPART (arg1); 1824 imag = const_binop (code, i1, i2, notrunc); 1830 const_binop (MULT_EXPR, i1, i2, notrunc), 1834 const_binop (MULT_EXPR, i1, r2, notrunc), 1848 const_binop (MULT_EXPR, i1, i2, notrunc), 1852 const_binop (MULT_EXPR, i1, r2, notrunc), 8740 /* Try replacing &a[i1] + c * i2 with &a[i1 + i2], if c is step 9125 /* Try replacing &a[i1] - c * i2 with &a[i1 1803 tree i1 = TREE_IMAGPART (arg1); local [all...] |
/freebsd-10.0-release/contrib/sqlite3/ |
H A D | sqlite3.c | 72597 int i1; local 121247 sqlite3_int64 i1 = 0; /* Last position from pp1 */ local 121583 sqlite3_int64 i1 = 0; local 121675 sqlite3_int64 i1 = 0; local [all...] |
/freebsd-10.0-release/crypto/heimdal/lib/sqlite/ |
H A D | sqlite3.c | 70620 int i1; local 115931 sqlite3_int64 i1 = 0; /* Last position from pp1 */ local 116273 sqlite3_int64 i1 = 0; local 116365 sqlite3_int64 i1 = 0; local [all...] |
/freebsd-10.0-release/contrib/gcc/config/i386/ |
H A D | i386.c | 18784 rtx neglab, donelab, i0, i1, f0, in, out; 18795 i1 = gen_reg_rtx (Pmode); 18807 i1 = expand_simple_binop (Pmode, AND, in, const1_rtx, NULL, 1, OPTAB_DIRECT); 18808 i0 = expand_simple_binop (Pmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT); 18753 rtx neglab, donelab, i0, i1, f0, in, out; local
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