Searched refs:i1 (Results 101 - 125 of 150) sorted by relevance

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/freebsd-10.0-release/contrib/gcc/cp/
H A Ddecl2.c318 tree p1, p2, i1, i2;
334 i1 = build_expr_type_conversion (WANT_INT | WANT_ENUM, array_expr,
339 if ((p1 && i2) && (i1 && p2))
344 else if (i1 && p2)
345 array_expr = p2, index_exp = i1;
317 tree p1, p2, i1, i2; local
/freebsd-10.0-release/contrib/llvm/tools/clang/lib/Analysis/
H A DThreadSafety.cpp1219 unsigned i1 = I.getData(); local
1223 else if (*i2 != i1) // variable exists, but has different definition
1248 unsigned i1 = I.getData(); local
1249 VarDefinition *VDef = &VarDefinitions[i1];
1253 if (!i2 || (*i2 != i1))
/freebsd-10.0-release/contrib/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp1157 for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
1158 e1 = SRM1.end(); i1 != e1; ++i1) {
1159 CodeGenSubRegIndex *Idx1 = i1->first;
1160 CodeGenRegister *Reg2 = i1->second;
H A DCodeGenTarget.cpp54 case MVT::i1: return "MVT::i1";
/freebsd-10.0-release/sys/sparc64/sparc64/
H A Dexception.S123 storer %i1, [base + (9 * size)] asi ; \
141 loader [base + (9 * size)] asi, %i1 ; \
2353 stx %i1, [%sp + SPOFF + CCFSZ + TF_O1]
2451 stx %i1, [%sp + SPOFF + CCFSZ + TF_O1]
2546 ldx [%sp + SPOFF + CCFSZ + TF_O1], %i1
2832 stx %i1, [%sp + SPOFF + CCFSZ + TF_O1]
2853 ldx [%sp + SPOFF + CCFSZ + TF_O1], %i1
/freebsd-10.0-release/contrib/gdb/gdb/
H A Dtracepoint.c2268 char *i1 = " ", *i2 = " "; local
2303 indent = i1;
2322 indent = i1;
/freebsd-10.0-release/contrib/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp73 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
82 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
485 MVT::i1,
H A DAMDILISelLowering.cpp199 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);
/freebsd-10.0-release/contrib/gcc/
H A Dvar-tracking.c1035 const struct variable_union_info *i1 = n1; local
1038 if (i1->pos != i2->pos)
1039 return i1->pos - i2->pos;
1041 return (i1->pos_dst - i2->pos_dst);
H A Dtree-vrp.c4188 unsigned i1, i2; local
4221 EXECUTE_IF_SET_IN_BITMAP (e1, 0, i1, bi1)
4223 value_range_t vr1 = *(vr_value[i1]);
4229 vr1.min = ssa_name (i1);
4230 vr1.max = ssa_name (i1);
H A Demit-rtl.c444 immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, enum machine_mode mode)
455 the integer fits into HOST_WIDE_INT anyway (i.e., i1 consists only
456 from copies of the sign bit, and sign of i0 and i1 are the same), then
458 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */
474 if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0))
482 CONST_DOUBLE_HIGH (value) = i1;
443 immed_double_const(HOST_WIDE_INT i0, HOST_WIDE_INT i1, enum machine_mode mode) argument
/freebsd-10.0-release/contrib/llvm/tools/clang/lib/Sema/
H A DSemaCast.cpp518 for (SmallVector<Qualifiers, 8>::reverse_iterator i1 = cv1.rbegin(),
520 i1 != cv1.rend(); ++i1, ++i2) {
522 = Context.getPointerType(Context.getQualifiedType(SrcConstruct, *i1));
H A DSemaDeclObjC.cpp2582 for (AttrVec::const_iterator i1 = D.begin(), e1 = D.end(); i1 != e1; ++i1) {
2583 if ((*i)->getKind() == (*i1)->getKind()) {
/freebsd-10.0-release/contrib/gcc/config/sparc/
H A Dsparc.c6163 rtx neglab, donelab, i0, i1, f0, in, out;
6170 i1 = gen_reg_rtx (DImode);
6182 emit_insn (gen_anddi3 (i1, in, const1_rtx)); local
6183 emit_insn (gen_iordi3 (i0, i0, i1));
6196 rtx neglab, donelab, i0, i1, f0, in, out, limit;
6203 i1 = gen_reg_rtx (DImode);
6224 emit_insn (gen_movdi (i1, const1_rtx));
6225 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
6226 emit_insn (gen_xordi3 (out, i0, i1));
6149 rtx neglab, donelab, i0, i1, f0, in, out; local
[all...]
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp273 Cond, DAG.getValueType(MVT::i1));
309 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
336 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
1366 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1367 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
/freebsd-10.0-release/contrib/llvm/lib/Transforms/Utils/
H A DSimplifyCFG.cpp602 unsigned i1 = 0, i2 = 0, e1 = V1->size(), e2 = V2->size(); local
603 while (i1 != e1 && i2 != e2) {
604 if ((*V1)[i1].Value == (*V2)[i2].Value)
606 if ((*V1)[i1].Value < (*V2)[i2].Value)
607 ++i1;
1348 /// br i1 %cmp, label %EndBB, label %ThenBB
1359 /// %add.add5 = select i1 %cmp, i32 %add, %add5
1417 /// br i1 %cmp, label %EndBB, label %ThenBB
1431 /// %cond = select i1 %cmp, 0, %sub
1779 // Don't fold i1 branche
[all...]
/freebsd-10.0-release/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp129 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
130 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
131 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
/freebsd-10.0-release/crypto/openssh/
H A Dssh-keygen.c396 int magic, rlen, ktype, i1, i2, i3, i4; local
409 i1 = buffer_get_int(&b);
415 debug("ignore (%d %d %d %d)", i1, i2, i3, i4);
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp882 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
899 IntReg >= (unsigned)MVT::i1; --IntReg) {
1064 // <4 x i1> -> <4 x i32>.
/freebsd-10.0-release/contrib/ee/
H A Dee.c938 int i1, i2; local
944 i1 = tabshift(column);
946 (i2 < i1) && (((column+i2+1)-horiz_offset) < last_col); i2++)
950 return(i1);
/freebsd-10.0-release/contrib/libreadline/
H A Dvi_mode.c1310 _rl_callback_data->i1 = _rl_cs_dir;
/freebsd-10.0-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp181 // We have native instructions for i8, i16 and i32 extensions, but not i1.
182 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
183 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
184 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
185 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
/freebsd-10.0-release/crypto/heimdal/lib/asn1/
H A Dcheck-gen.c788 c1.u.i1 = 1;
/freebsd-10.0-release/sys/dev/advansys/
H A Dadvlib.h754 struct adv_scsiq_1 i1; member in struct:adv_risc_q
/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp215 // Mips does not have i1 type, so use i32 for
220 // Load extented operations for i1 types must be promoted
221 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
222 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
223 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
233 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
299 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);

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