/freebsd-10.0-release/contrib/gcc/cp/ |
H A D | decl2.c | 318 tree p1, p2, i1, i2; 334 i1 = build_expr_type_conversion (WANT_INT | WANT_ENUM, array_expr, 339 if ((p1 && i2) && (i1 && p2)) 344 else if (i1 && p2) 345 array_expr = p2, index_exp = i1; 317 tree p1, p2, i1, i2; local
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/freebsd-10.0-release/contrib/llvm/tools/clang/lib/Analysis/ |
H A D | ThreadSafety.cpp | 1219 unsigned i1 = I.getData(); local 1223 else if (*i2 != i1) // variable exists, but has different definition 1248 unsigned i1 = I.getData(); local 1249 VarDefinition *VDef = &VarDefinitions[i1]; 1253 if (!i2 || (*i2 != i1))
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/freebsd-10.0-release/contrib/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 1157 for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(), 1158 e1 = SRM1.end(); i1 != e1; ++i1) { 1159 CodeGenSubRegIndex *Idx1 = i1->first; 1160 CodeGenRegister *Reg2 = i1->second;
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H A D | CodeGenTarget.cpp | 54 case MVT::i1: return "MVT::i1";
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/freebsd-10.0-release/sys/sparc64/sparc64/ |
H A D | exception.S | 123 storer %i1, [base + (9 * size)] asi ; \ 141 loader [base + (9 * size)] asi, %i1 ; \ 2353 stx %i1, [%sp + SPOFF + CCFSZ + TF_O1] 2451 stx %i1, [%sp + SPOFF + CCFSZ + TF_O1] 2546 ldx [%sp + SPOFF + CCFSZ + TF_O1], %i1 2832 stx %i1, [%sp + SPOFF + CCFSZ + TF_O1] 2853 ldx [%sp + SPOFF + CCFSZ + TF_O1], %i1
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/freebsd-10.0-release/contrib/gdb/gdb/ |
H A D | tracepoint.c | 2268 char *i1 = " ", *i2 = " "; local 2303 indent = i1; 2322 indent = i1;
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/freebsd-10.0-release/contrib/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.cpp | 73 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom); 82 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom); 485 MVT::i1,
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H A D | AMDILISelLowering.cpp | 199 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);
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/freebsd-10.0-release/contrib/gcc/ |
H A D | var-tracking.c | 1035 const struct variable_union_info *i1 = n1; local 1038 if (i1->pos != i2->pos) 1039 return i1->pos - i2->pos; 1041 return (i1->pos_dst - i2->pos_dst);
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H A D | tree-vrp.c | 4188 unsigned i1, i2; local 4221 EXECUTE_IF_SET_IN_BITMAP (e1, 0, i1, bi1) 4223 value_range_t vr1 = *(vr_value[i1]); 4229 vr1.min = ssa_name (i1); 4230 vr1.max = ssa_name (i1);
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H A D | emit-rtl.c | 444 immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, enum machine_mode mode) 455 the integer fits into HOST_WIDE_INT anyway (i.e., i1 consists only 456 from copies of the sign bit, and sign of i0 and i1 are the same), then 458 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */ 474 if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0)) 482 CONST_DOUBLE_HIGH (value) = i1; 443 immed_double_const(HOST_WIDE_INT i0, HOST_WIDE_INT i1, enum machine_mode mode) argument
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/freebsd-10.0-release/contrib/llvm/tools/clang/lib/Sema/ |
H A D | SemaCast.cpp | 518 for (SmallVector<Qualifiers, 8>::reverse_iterator i1 = cv1.rbegin(), 520 i1 != cv1.rend(); ++i1, ++i2) { 522 = Context.getPointerType(Context.getQualifiedType(SrcConstruct, *i1));
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H A D | SemaDeclObjC.cpp | 2582 for (AttrVec::const_iterator i1 = D.begin(), e1 = D.end(); i1 != e1; ++i1) { 2583 if ((*i)->getKind() == (*i1)->getKind()) {
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/freebsd-10.0-release/contrib/gcc/config/sparc/ |
H A D | sparc.c | 6163 rtx neglab, donelab, i0, i1, f0, in, out; 6170 i1 = gen_reg_rtx (DImode); 6182 emit_insn (gen_anddi3 (i1, in, const1_rtx)); local 6183 emit_insn (gen_iordi3 (i0, i0, i1)); 6196 rtx neglab, donelab, i0, i1, f0, in, out, limit; 6203 i1 = gen_reg_rtx (DImode); 6224 emit_insn (gen_movdi (i1, const1_rtx)); 6225 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63))); 6226 emit_insn (gen_xordi3 (out, i0, i1)); 6149 rtx neglab, donelab, i0, i1, f0, in, out; local [all...] |
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 273 Cond, DAG.getValueType(MVT::i1)); 309 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); 336 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, 1366 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements); 1367 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
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/freebsd-10.0-release/contrib/llvm/lib/Transforms/Utils/ |
H A D | SimplifyCFG.cpp | 602 unsigned i1 = 0, i2 = 0, e1 = V1->size(), e2 = V2->size(); local 603 while (i1 != e1 && i2 != e2) { 604 if ((*V1)[i1].Value == (*V2)[i2].Value) 606 if ((*V1)[i1].Value < (*V2)[i2].Value) 607 ++i1; 1348 /// br i1 %cmp, label %EndBB, label %ThenBB 1359 /// %add.add5 = select i1 %cmp, i32 %add, %add5 1417 /// br i1 %cmp, label %EndBB, label %ThenBB 1431 /// %cond = select i1 %cmp, 0, %sub 1779 // Don't fold i1 branche [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 129 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 130 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 131 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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/freebsd-10.0-release/crypto/openssh/ |
H A D | ssh-keygen.c | 396 int magic, rlen, ktype, i1, i2, i3, i4; local 409 i1 = buffer_get_int(&b); 415 debug("ignore (%d %d %d %d)", i1, i2, i3, i4);
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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 882 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 899 IntReg >= (unsigned)MVT::i1; --IntReg) { 1064 // <4 x i1> -> <4 x i32>.
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/freebsd-10.0-release/contrib/ee/ |
H A D | ee.c | 938 int i1, i2; local 944 i1 = tabshift(column); 946 (i2 < i1) && (((column+i2+1)-horiz_offset) < last_col); i2++) 950 return(i1);
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/freebsd-10.0-release/contrib/libreadline/ |
H A D | vi_mode.c | 1310 _rl_callback_data->i1 = _rl_cs_dir;
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/freebsd-10.0-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 181 // We have native instructions for i8, i16 and i32 extensions, but not i1. 182 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 183 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 184 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 185 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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/freebsd-10.0-release/crypto/heimdal/lib/asn1/ |
H A D | check-gen.c | 788 c1.u.i1 = 1;
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/freebsd-10.0-release/sys/dev/advansys/ |
H A D | advlib.h | 754 struct adv_scsiq_1 i1; member in struct:adv_risc_q
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/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 215 // Mips does not have i1 type, so use i32 for 220 // Load extented operations for i1 types must be promoted 221 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 222 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 223 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 233 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 299 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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