Searched refs:x2 (Results 51 - 75 of 1124) sorted by relevance

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/freebsd-10-stable/sys/gnu/dts/arm/
H A Dimx25-pdk.dts216 MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN)
220 MATRIX_KEY(0x1, 0x2, KEY_ENTER)
222 MATRIX_KEY(0x2, 0x0, KEY_F6)
223 MATRIX_KEY(0x2, 0x1, KEY_F8)
224 MATRIX_KEY(0x2, 0x2, KEY_F9)
225 MATRIX_KEY(0x2, 0x3, KEY_F10)
228 MATRIX_KEY(0x3, 0x2, KEY_F3)
229 MATRIX_KEY(0x3, 0x2, KEY_POWER)
H A Dimx6sx-pinfunc.h19 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
27 #define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK 0x0018 0x0360 0x0000 0x2 0x0
35 #define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK 0x001C 0x0364 0x0000 0x2 0x0
43 #define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0x0020 0x0368 0x0000 0x2 0x0
52 #define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0
61 #define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0
70 #define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0
79 #define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0
88 #define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0
97 #define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2
[all...]
H A Dimx50-pinfunc.h19 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
24 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
29 #define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0 0x028 0x2d4 0x000 0x2 0x0
34 #define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1 0x02c 0x2d8 0x000 0x2 0x0
39 #define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2 0x030 0x2dc 0x000 0x2 0x0
44 #define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3 0x034 0x2e0 0x000 0x2 0x0
49 #define MX50_PAD_KEY_COL3__EIM_NANDF_READY0 0x038 0x2e4 0x7b4 0x2 0x0
54 #define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS 0x03c 0x2e8 0x7b0 0x2 0x0
59 #define MX50_PAD_I2C1_SCL__UART2_TXD_MUX 0x040 0x2ec 0x7cc 0x2 0x0
62 #define MX50_PAD_I2C1_SDA__UART2_RXD_MUX 0x044 0x2f0 0x7cc 0x2
[all...]
/freebsd-10-stable/crypto/openssl/crypto/rc2/
H A Drc2_locl.h148 t=(x0+(x1& ~x3)+(x2&x3)+ *(p0++))&0xffff; \
150 t=(x1+(x2& ~x0)+(x3&x0)+ *(p0++))&0xffff; \
152 t=(x2+(x3& ~x1)+(x0&x1)+ *(p0++))&0xffff; \
153 x2=(t<<3)|(t>>13); \
154 t=(x3+(x0& ~x2)+(x1&x2)+ *(p0++))&0xffff; \
/freebsd-10-stable/sys/arm/ti/
H A Dti_sdma.h48 #define TI_SDMA_BURST_32 0x2
53 #define TI_SDMA_DATA_32BITS_SCALAR 0x2
57 #define TI_SDMA_ADDR_SINGLE_INDEX 0x2
/freebsd-10-stable/sys/isa/
H A Dpnpreg.h170 #define PNP_MEM_CONTROL_16BIT 0x2
229 #define PNP_TAG_LOGICAL_DEVICE 0x2
243 #define PNP_TAG_ID_ANSI 0x2
/freebsd-10-stable/contrib/apr/include/
H A Dapr_thread_mutex.h45 #define APR_THREAD_MUTEX_UNNESTED 0x2 /**< disable nested locks */
/freebsd-10-stable/contrib/binutils/include/opcode/
H A Ds390.h114 #define S390_OPERAND_FPR 0x2
/freebsd-10-stable/include/
H A Dwordexp.h52 #define WRDE_DOOFFS 0x2 /* we_offs member is valid */
/freebsd-10-stable/sys/cam/scsi/
H A Dscsi_iu.h12 #define SIU_SNSVALID 0x2
/freebsd-10-stable/sys/contrib/octeon-sdk/
H A Dcvmx-helper-board.h78 set_phy_link_flags_flow_control_disable = 0x2 << 1,
H A Dcvmx-rtc.h69 CVMX_RTC_WRITE = 0x2, /**< Device supports write access */
/freebsd-10-stable/sys/dev/nand/
H A Dnandsim_swap.h40 #define BLOCK_SWAPPED 0x2
/freebsd-10-stable/sys/fs/nfs/
H A Dnfscl.h67 #define NFSSATTR_SIZE0 0x2
/freebsd-10-stable/sys/mips/atheros/
H A Dpcf2123reg.h38 #define PCF2123_REG_SECONDS 0x2
/freebsd-10-stable/sys/sys/
H A Dstatvfs.h75 #define ST_NOSUID 0x2
/freebsd-10-stable/usr.sbin/bhyve/
H A Dmem.h49 #define MEM_F_WRITE 0x2
/freebsd-10-stable/contrib/ntp/lib/isc/include/isc/
H A Dfsaccess.h140 #define ISC_FSACCESS_GROUP 0x2 /*%< Primary group owner. */
/freebsd-10-stable/bin/sh/
H A Dparser.h57 #define VSMINUS 0x2 /* ${var-text} */
/freebsd-10-stable/contrib/ntp/ntpdc/
H A Dntpdc.h23 #define NTP_UINT 0x2 /* unsigned integer */
/freebsd-10-stable/sys/boot/fdt/dts/powerpc/
H A Dmpc8555cds.dts113 0x2 0x0 0xf8000000 0x00008000>;
137 reg = <0x2 0x0 0x00008000>;
356 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
357 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
362 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
363 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
368 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
369 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
374 0x9800 0x0 0x0 0x2 &mpic 0x2
[all...]
/freebsd-10-stable/sys/dev/vxge/vxgehal/
H A Dvxgehal-regs.h608 #define VXGE_HAL_PCI_EXP_LNKCAP_LS_5 0x2 /* 5 and 2.5 Gb/s supported. */
612 #define VXGE_HAL_PCI_EXP_LNKCAP_LW_X2 0x2 /* Reserved. */
621 #define VXGE_HAL_PCI_EXP_LNKCAP_LASPM_RES2 0x2 /* Reserved. */
626 #define VXGE_HAL_PCI_EXP_LNKCAP_L0_128_256 0x2 /* 128ns to less than 256ns. */
635 #define VXGE_HAL_PCI_EXP_LNKCAP_L1_2us_4us 0x2 /* 2us to less than 4us. */
650 #define VXGE_HAL_PCI_EXP_LNKCTL_ASPM_L1_EN 0x2 /* L1 entry enabled. */
666 #define VXGE_HAL_PCI_EXP_LNKSTA_LS_5 0x2 /* 5 2.5 Gb/s supported. */
670 #define VXGE_HAL_PCI_EXP_LNKSTA_LW_X2 0x2 /* Reserved. */
683 #define VXGE_HAL_PCI_EXP_STLCAP_PWR_CTRL 0x2 /* Power Control Present */
696 #define VXGE_HAL_PCI_EXP_STLCAP_SL_PWR_XBY100 0x2 /* 0.0
[all...]
/freebsd-10-stable/lib/msun/ld80/
H A Ds_expl.c164 long double x_lo, x2, z; local
203 x2 = x * x;
204 x4 = x2 * x2;
205 q = x4 * (x2 * (x4 *
211 (x2 * B12 + (x * B11 + B10)) +
212 (x2 * (x * B9 + B8) + (x * B7 + B6))) +
213 (x * B5 + B4.e)) + x2 * x * B3.e;
/freebsd-10-stable/sys/arm/xscale/ixp425/
H A Dixp425_pci_asm.S66 eor r1, r1, #0x2
97 eor r1, r1, #0x2
/freebsd-10-stable/sys/dev/ic/
H A Dvia6522reg.h56 #define ACR_SRI_PHI2 0x2 /* " " " " " PHI2 */
73 #define PCR_CNTL_PEDGE 0x2 /* Input - positive active edge */

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