/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/sound/pci/pcxhr/ |
H A D | pcxhr_mix22.c | 413 enum pcxhr_clock_type clock_type, 420 if (clock_type == HR22_CLOCK_TYPE_AES_SYNC) { 426 } else if (clock_type == HR22_CLOCK_TYPE_AES_1 && mgr->board_has_aes1) { 434 clock_type); 439 snd_printdd("get_external_clock(%d) = 0 Hz\n", clock_type); 412 hr222_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type, int *sample_rate) argument
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H A D | pcxhr.c | 403 enum pcxhr_clock_type clock_type, 410 switch (clock_type) { 466 enum pcxhr_clock_type clock_type, 470 return hr222_get_external_clock(mgr, clock_type, 473 return pcxhr_sub_get_external_clock(mgr, clock_type, 402 pcxhr_sub_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type, int *sample_rate) argument 465 pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type, int *sample_rate) argument
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/net/wan/ |
H A D | ixp4xx_hss.c | 263 unsigned int clock_type, clock_rate, loopback; member in struct:port 401 if (port->clock_type == CLOCK_INT) 1257 new_line.clock_type = port->clock_type; 1271 clk = new_line.clock_type; 1281 port->clock_type = clk; /* Update settings */ 1347 port->clock_type = CLOCK_EXT;
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H A D | wanxl.c | 59 unsigned int clock_type; member in struct:__anon17383 356 line.clock_type = get_status(port)->clocking; 374 if (line.clock_type != CLOCK_EXT && 375 line.clock_type != CLOCK_TXFROMRX) 381 get_status(port)->clocking = line.clock_type;
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H A D | farsync.c | 1919 switch (sync.clock_type) { 1977 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==
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H A D | pc300_drv.c | 618 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */ 782 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */ 2641 u32 clktype = chan->conf.phys_settings.clock_type; 3114 chan->conf.phys_settings.clock_type = CLOCK_EXT;
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H A D | dscc4.c | 957 if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/wan/ |
H A D | ixp4xx_hss.c | 263 unsigned int clock_type, clock_rate, loopback; member in struct:port 401 if (port->clock_type == CLOCK_INT) 1257 new_line.clock_type = port->clock_type; 1271 clk = new_line.clock_type; 1281 port->clock_type = clk; /* Update settings */ 1347 port->clock_type = CLOCK_EXT;
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H A D | wanxl.c | 59 unsigned int clock_type; member in struct:__anon29076 356 line.clock_type = get_status(port)->clocking; 374 if (line.clock_type != CLOCK_EXT && 375 line.clock_type != CLOCK_TXFROMRX) 381 get_status(port)->clocking = line.clock_type;
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H A D | farsync.c | 1919 switch (sync.clock_type) { 1977 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==
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H A D | pc300_drv.c | 618 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */ 782 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */ 2641 u32 clktype = chan->conf.phys_settings.clock_type; 3114 chan->conf.phys_settings.clock_type = CLOCK_EXT;
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H A D | dscc4.c | 957 if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-ixp4xx/ |
H A D | goramo_mlr.c | 131 static int hss_set_clock(int port, unsigned int clock_type) argument 135 switch (clock_type) {
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-ixp4xx/ |
H A D | goramo_mlr.c | 131 static int hss_set_clock(int port, unsigned int clock_type) argument 135 switch (clock_type) {
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/sound/pci/pcxhr/ |
H A D | pcxhr.c | 403 enum pcxhr_clock_type clock_type, 410 switch (clock_type) { 466 enum pcxhr_clock_type clock_type, 470 return hr222_get_external_clock(mgr, clock_type, 473 return pcxhr_sub_get_external_clock(mgr, clock_type, 402 pcxhr_sub_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type, int *sample_rate) argument 465 pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type, int *sample_rate) argument
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/video/ |
H A D | sm501fb.c | 416 unsigned int clock_type; local 427 clock_type = SM501_CLOCK_V2XCLK; 433 clock_type = SM501_CLOCK_P2XCLK; 440 clock_type = 0; 485 sm501pixclock = sm501_set_clock(fbi->dev->parent, clock_type,
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/video/ |
H A D | sm501fb.c | 416 unsigned int clock_type; local 427 clock_type = SM501_CLOCK_V2XCLK; 433 clock_type = SM501_CLOCK_P2XCLK; 440 clock_type = 0; 485 sm501pixclock = sm501_set_clock(fbi->dev->parent, clock_type,
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/char/pcmcia/ |
H A D | synclink_cs.c | 4145 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 4146 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 4147 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 4148 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 4149 default: new_line.clock_type = CLOCK_DEFAULT; 4166 switch (new_line.clock_type)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/char/pcmcia/ |
H A D | synclink_cs.c | 4145 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 4146 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 4147 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 4148 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 4149 default: new_line.clock_type = CLOCK_DEFAULT; 4166 switch (new_line.clock_type)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/char/ |
H A D | synclink.c | 7845 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 7846 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 7847 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 7848 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 7849 default: new_line.clock_type = CLOCK_DEFAULT; 7866 switch (new_line.clock_type)
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H A D | synclink_gt.c | 1634 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 1635 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 1636 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 1637 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 1638 default: new_line.clock_type = CLOCK_DEFAULT; 1655 switch (new_line.clock_type)
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H A D | synclinkmp.c | 1771 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 1772 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 1773 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 1774 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 1775 default: new_line.clock_type = CLOCK_DEFAULT; 1792 switch (new_line.clock_type)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/char/ |
H A D | synclink.c | 7845 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 7846 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 7847 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 7848 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 7849 default: new_line.clock_type = CLOCK_DEFAULT; 7866 switch (new_line.clock_type)
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H A D | synclink_gt.c | 1634 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 1635 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 1636 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 1637 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 1638 default: new_line.clock_type = CLOCK_DEFAULT; 1655 switch (new_line.clock_type)
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H A D | synclinkmp.c | 1771 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 1772 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 1773 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 1774 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 1775 default: new_line.clock_type = CLOCK_DEFAULT; 1792 switch (new_line.clock_type)
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