Searched refs:__REG (Results 51 - 60 of 60) sorted by relevance
123
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/sound/soc/pxa/ |
H A D | pxa2xx-i2s.c | 36 #define SACR0 __REG(0x40400000) /* Global Control Register */ 37 #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ 38 #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ 39 #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */ 40 #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */ 41 #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ 42 #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/sound/soc/pxa/ |
H A D | pxa2xx-i2s.c | 36 #define SACR0 __REG(0x40400000) /* Global Control Register */ 37 #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ 38 #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ 39 #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */ 40 #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */ 41 #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ 42 #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-pxa/include/mach/ |
H A D | hardware.h | 42 # define __REG(x) (*((volatile u32 *)io_p2v(x))) macro 47 (*(volatile u32 *)((u32)&__REG(x) + (y))) 53 # define __REG(x) io_p2v(x) macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-pxa/include/mach/ |
H A D | hardware.h | 42 # define __REG(x) (*((volatile u32 *)io_p2v(x))) macro 47 (*(volatile u32 *)((u32)&__REG(x) + (y))) 53 # define __REG(x) io_p2v(x) macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-ns9xxx/include/mach/ |
H A D | hardware.h | 36 # define __REG(x) ((void __iomem __force *)io_p2v((x))) macro 72 # define __REG(x) io_p2v(x) macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-ns9xxx/include/mach/ |
H A D | hardware.h | 36 # define __REG(x) ((void __iomem __force *)io_p2v((x))) macro 72 # define __REG(x) io_p2v(x) macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/net/irda/ |
H A D | pxaficp_ir.c | 33 #define FICP __REG(0x40800000) /* Start of FICP area */ 34 #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ 35 #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ 36 #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ 37 #define ICDR __REG(0x4080000c) /* ICP Data Register */ 38 #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ 39 #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/irda/ |
H A D | pxaficp_ir.c | 33 #define FICP __REG(0x40800000) /* Start of FICP area */ 34 #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ 35 #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ 36 #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ 37 #define ICDR __REG(0x4080000c) /* ICP Data Register */ 38 #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ 39 #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/xtensa/include/asm/ |
H A D | coprocessor.h | 117 __REG ## list (cc, abi, type, name, size, align)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/xtensa/include/asm/ |
H A D | coprocessor.h | 117 __REG ## list (cc, abi, type, name, size, align)
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