Searched refs:__REG (Results 26 - 50 of 60) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-ns9xxx/include/mach/
H A Dregs-sys-common.h23 #define SYS_ISRADDR __REG(0xa0900164)
26 #define SYS_ISA __REG(0xa0900168)
29 #define SYS_ISR __REG(0xa090016c)
H A Dregs-board-a9m9750dev.h21 #define FPGA_IER __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50)
22 #define FPGA_ISR __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60)
H A Duncompress.h16 #define __REG(x) ((void __iomem __force *)(x)) macro
68 #define MSCS __REG(0xA0900184)
70 #define NS9360_UARTA __REG(0x90200040)
71 #define NS9360_UARTB __REG(0x90200000)
72 #define NS9360_UARTC __REG(0x90300000)
73 #define NS9360_UARTD __REG(0x90300040)
78 #define A9M9750DEV_UARTA __REG(0x40000000)
80 #define NS921XSYS_CLOCK __REG(0xa090017c)
81 #define NS921X_UARTA __REG(0x90010000)
82 #define NS921X_UARTB __REG(
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H A Dregs-bbu.h37 #define BBU_GCTRL1 __REG(0x90600030)
38 #define BBU_GCTRL2 __REG(0x90600034)
39 #define BBU_GCTRL3 __REG(0x90600120)
41 #define BBU_GSTAT1 __REG(0x90600040)
42 #define BBU_GSTAT2 __REG(0x90600044)
43 #define BBU_GSTAT3 __REG(0x90600130)
H A Dregs-sys-ns9360.h19 #define SYS_AHBAGENCONF __REG(0xa0900000)
31 #define SYS_TIS __REG(0xa0900170)
34 #define SYS_PLL __REG(0xa0900188)
127 #define SYS_GENID __REG(0xa0900210)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-lh7a40x/include/mach/
H A Ddma.h26 #define DMAC_GCA __REG(DMAC_PHYS + 0x2b80)
27 #define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0)
55 #define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00)
56 #define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04)
57 #define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08)
58 #define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c)
59 #define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14)
60 #define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20)
61 #define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24)
62 #define DMAC_P_CURRENT0(c) __REG(DMAC_PHY
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H A Dhardware.h23 # define __REG(x) io_p2v(x) macro
29 * This __REG() version gives the same results as the one above, except
37 # define __REG(x) __REGP(io_p2v(x)) macro
47 ( __builtin_constant_p(y) ? (__REG((x) + (y))) \
48 : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-lh7a40x/include/mach/
H A Ddma.h26 #define DMAC_GCA __REG(DMAC_PHYS + 0x2b80)
27 #define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0)
55 #define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00)
56 #define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04)
57 #define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08)
58 #define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c)
59 #define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14)
60 #define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20)
61 #define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24)
62 #define DMAC_P_CURRENT0(c) __REG(DMAC_PHY
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H A Dhardware.h23 # define __REG(x) io_p2v(x) macro
29 * This __REG() version gives the same results as the one above, except
37 # define __REG(x) __REGP(io_p2v(x)) macro
47 ( __builtin_constant_p(y) ? (__REG((x) + (y))) \
48 : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-ns9xxx/include/mach/
H A Dregs-board-a9m9750dev.h21 #define FPGA_IER __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50)
22 #define FPGA_ISR __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60)
H A Duncompress.h16 #define __REG(x) ((void __iomem __force *)(x)) macro
68 #define MSCS __REG(0xA0900184)
70 #define NS9360_UARTA __REG(0x90200040)
71 #define NS9360_UARTB __REG(0x90200000)
72 #define NS9360_UARTC __REG(0x90300000)
73 #define NS9360_UARTD __REG(0x90300040)
78 #define A9M9750DEV_UARTA __REG(0x40000000)
80 #define NS921XSYS_CLOCK __REG(0xa090017c)
81 #define NS921X_UARTA __REG(0x90010000)
82 #define NS921X_UARTB __REG(
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H A Dregs-bbu.h37 #define BBU_GCTRL1 __REG(0x90600030)
38 #define BBU_GCTRL2 __REG(0x90600034)
39 #define BBU_GCTRL3 __REG(0x90600120)
41 #define BBU_GSTAT1 __REG(0x90600040)
42 #define BBU_GSTAT2 __REG(0x90600044)
43 #define BBU_GSTAT3 __REG(0x90600130)
H A Dregs-sys-ns9360.h19 #define SYS_AHBAGENCONF __REG(0xa0900000)
31 #define SYS_TIS __REG(0xa0900170)
34 #define SYS_PLL __REG(0xa0900188)
127 #define SYS_GENID __REG(0xa0900210)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h110 #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */
111 #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */
112 #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */
113 #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */
114 #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */
115 #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
116 #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
117 #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */
118 #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */
119 #define Ser0UDCDR __REG(
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H A Dhardware.h59 # define __REG(x) (*((volatile unsigned long *)io_p2v(x))) macro
68 # define __REG(x) io_p2v(x) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h110 #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */
111 #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */
112 #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */
113 #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */
114 #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */
115 #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
116 #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
117 #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */
118 #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */
119 #define Ser0UDCDR __REG(
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H A Dhardware.h59 # define __REG(x) (*((volatile unsigned long *)io_p2v(x))) macro
68 # define __REG(x) io_p2v(x) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-aaec2000/include/mach/
H A Dhardware.h37 #define __REG(x) (*((volatile u32 *)io_p2v(x))) macro
42 #define __REG(x) io_p2v(x) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-aaec2000/include/mach/
H A Dhardware.h37 #define __REG(x) (*((volatile u32 *)io_p2v(x))) macro
42 #define __REG(x) io_p2v(x) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-dove/include/mach/
H A Dhardware.h22 #define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-pxa/include/mach/
H A Dpxa27x.h8 #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-dove/include/mach/
H A Dhardware.h22 #define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-pxa/include/mach/
H A Dpxa27x.h8 #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-lh7a40x/
H A Dclcd.c31 #define HRTFTC_HRSETUP __REG(HRTFTC_PHYS + 0x00)
32 #define HRTFTC_HRCON __REG(HRTFTC_PHYS + 0x04)
33 #define HRTFTC_HRTIMING1 __REG(HRTFTC_PHYS + 0x08)
34 #define HRTFTC_HRTIMING2 __REG(HRTFTC_PHYS + 0x0c)
36 #define ALI_SETUP __REG(ALI_PHYS + 0x00)
37 #define ALI_CONTROL __REG(ALI_PHYS + 0x04)
38 #define ALI_TIMING1 __REG(ALI_PHYS + 0x08)
39 #define ALI_TIMING2 __REG(ALI_PHYS + 0x0c)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-lh7a40x/
H A Dclcd.c31 #define HRTFTC_HRSETUP __REG(HRTFTC_PHYS + 0x00)
32 #define HRTFTC_HRCON __REG(HRTFTC_PHYS + 0x04)
33 #define HRTFTC_HRTIMING1 __REG(HRTFTC_PHYS + 0x08)
34 #define HRTFTC_HRTIMING2 __REG(HRTFTC_PHYS + 0x0c)
36 #define ALI_SETUP __REG(ALI_PHYS + 0x00)
37 #define ALI_CONTROL __REG(ALI_PHYS + 0x04)
38 #define ALI_TIMING1 __REG(ALI_PHYS + 0x08)
39 #define ALI_TIMING2 __REG(ALI_PHYS + 0x0c)

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