Searched refs:SDRAM (Results 26 - 49 of 49) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/video/aty/
H A Dmach64_ct.c351 else if (par->ram_type >= SDRAM)
468 case SDRAM:
542 if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM))
H A Datyfb_base.c542 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
544 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
2388 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2389 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
3039 if ((aty_ld_le32(CNFG_STAT0, par) & 7) >= SDRAM)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/frv/kernel/
H A Dhead.S106 # we need to relocate the SDRAM to 0x00000000 (linux) or 0xC0000000 (uClinux)
108 # fiddling with the SDRAM controller registers
131 sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
138 # consult the SDRAM controller CS address registers
151 # assume the lowest valid CS line to be the SDRAM base and get its address
160 cor gr23,gr0,gr24, cc7,#1 ; GR24 = SDRAM base
165 # calculate the displacement required to get the SDRAM into the right place in memory
231 # move the kernel image down to the bottom of the SDRAM
423 # save the SDRAM details
564 # GR25 SDRAM siz
[all...]
H A Dhead-uc-fr451.S42 # GR25 SDRAM size [saved]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/frv/kernel/
H A Dhead.S106 # we need to relocate the SDRAM to 0x00000000 (linux) or 0xC0000000 (uClinux)
108 # fiddling with the SDRAM controller registers
131 sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
138 # consult the SDRAM controller CS address registers
151 # assume the lowest valid CS line to be the SDRAM base and get its address
160 cor gr23,gr0,gr24, cc7,#1 ; GR24 = SDRAM base
165 # calculate the displacement required to get the SDRAM into the right place in memory
231 # move the kernel image down to the bottom of the SDRAM
423 # save the SDRAM details
564 # GR25 SDRAM siz
[all...]
H A Dhead-uc-fr451.S42 # GR25 SDRAM size [saved]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-omap2/
H A Dsram34xx.S83 * before use by the code in SRAM (SDRAM is not accessible during SDRC
100 * SDRAM when the registers are written. If the registers are changed while
101 * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
104 * touching the SDRAM. Until that time, users who know that their use case
139 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
148 beq return_to_sdram @ return to SDRAM code, otherwise,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-omap2/
H A Dsram34xx.S83 * before use by the code in SRAM (SDRAM is not accessible during SDRC
100 * SDRAM when the registers are written. If the registers are changed while
101 * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
104 * touching the SDRAM. Until that time, users who know that their use case
139 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
148 beq return_to_sdram @ return to SDRAM code, otherwise,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-at91/
H A Dpm_slowclock.S31 #warning Assuming EB1 SDRAM controller is *NOT* used
113 * R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
126 /* Put SDRAM in self-refresh mode */
149 /* Enable SDRAM self-refresh mode */
274 /* Restore LPR on AT91 with SDRAM */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/cris/arch-v10/lib/
H A Ddram_init.S2 * DRAM/SDRAM initialization - alter with care
42 ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/cris/arch-v32/mach-fs/
H A Ddram_init.S2 * DRAM/SDRAM initialization - alter with care
25 ; Refer to BIF MDS for a description of SDRAM initialization
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/h8300/platform/h8s/edosk2674/
H A Dcrt0_rom.S43 ;SDRAM setup
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/h8300/platform/h8s/edosk2674/
H A Dcrt0_rom.S43 ;SDRAM setup
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-at91/
H A Dpm_slowclock.S31 #warning Assuming EB1 SDRAM controller is *NOT* used
113 * R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
126 /* Put SDRAM in self-refresh mode */
149 /* Enable SDRAM self-refresh mode */
274 /* Restore LPR on AT91 with SDRAM */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/cris/arch-v10/lib/
H A Ddram_init.S2 * DRAM/SDRAM initialization - alter with care
42 ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/cris/arch-v32/mach-fs/
H A Ddram_init.S2 * DRAM/SDRAM initialization - alter with care
25 ; Refer to BIF MDS for a description of SDRAM initialization
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/shared/
H A Dsbsdram.S2 * BCM47XX Sonics SiliconBackplane SDRAM/MEMC core initialization
221 /* Get SDRAM parameters (t0, t1, t2) from NVRAM (a2) */
223 lw t0,8(a2) # SDRAM init
226 andi t1,t2,0xffff # SDRAM config
227 srl t2,16 # SDRAM refresh
228 lw t3,16(a2) # SDRAM ncdl
252 /* Initialize DDR SDRAM */
886 /* Wait for SDRAM controller to refresh.
918 /* Initialize for SDR SDRAM */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/bcm91125e/src/
H A Dbcm91125e_init.S328 # Check memory type @ byte 2. 0x07(SDRAM DDR)
330 li t2,0x07 /*JEDEC SDRAM memory type*/
378 * 128MB on MC 1 (JEDEC SDRAM)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/carmel/src/
H A Dcarmel_init.S476 # Check memory type @ byte 2. 0x07(SDRAM DDR)
478 li t2,0x07 /*JEDEC SDRAM memory type*/
527 * 128MB on MC 1 (JEDEC SDRAM)
559 * 256MB on MC 1 (JEDEC SDRAM)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/xgifb/
H A Dvb_def.h418 #define SDRAM 000h macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/xgifb/
H A Dvb_def.h418 #define SDRAM 000h macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/include/video/
H A Dmach64.h885 #define SDRAM 4 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/include/video/
H A Dmach64.h885 #define SDRAM 4 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/video/aty/
H A Datyfb_base.c542 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
544 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
2388 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2389 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
3039 if ((aty_ld_le32(CNFG_STAT0, par) & 7) >= SDRAM)

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