Searched refs:R4600_V1_HIT_CACHEOP_WAR (Results 51 - 70 of 70) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-pnx833x/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-pnx8550/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-powertv/
H A Dwar.h15 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-rc32434/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-rm/
H A Dwar.h16 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-sead3/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-tx39xx/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-tx49xx/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-vr41xx/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-wrppmc/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-yosemite/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/pmc-sierra/msp71xx/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/mach-sibyte/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-sibyte/
H A Dwar.h12 #define R4600_V1_HIT_CACHEOP_WAR 0 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/
H A Dwar.h68 #ifndef R4600_V1_HIT_CACHEOP_WAR
69 #error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/
H A Dwar.h68 #ifndef R4600_V1_HIT_CACHEOP_WAR
69 #error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/mm/
H A Dpage.c260 if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
402 if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
H A Dc-r4k.c92 if (R4600_V1_HIT_CACHEOP_WAR) \
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/mm/
H A Dpage.c260 if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
402 if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
H A Dc-r4k.c92 if (R4600_V1_HIT_CACHEOP_WAR) \

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