Searched refs:MIPS_CPU_IRQ_BASE (Results 51 - 75 of 110) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/mti-malta/
H A Dmalta-time.c121 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
139 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
H A Dmalta-int.c282 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
301 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
306 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
534 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
536 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
551 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
552 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
556 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
557 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
609 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE
[all...]
H A Dmalta-platform.c50 .irq = MIPS_CPU_IRQ_BASE + 2,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/mti-malta/
H A Dmalta-time.c121 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
139 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
H A Dmalta-int.c282 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
301 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
306 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
534 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
536 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
551 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
552 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
556 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
557 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
609 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE
[all...]
H A Dmalta-platform.c50 .irq = MIPS_CPU_IRQ_BASE + 2,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/emma/markeins/
H A Dirq.c304 setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade);
312 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
316 do_IRQ(MIPS_CPU_IRQ_BASE + 1);
318 do_IRQ(MIPS_CPU_IRQ_BASE + 0);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/dec/
H A Dinterrupts.h91 #define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/sgi/
H A Dip22.h28 #define SGINT_CPU MIPS_CPU_IRQ_BASE /* MIPS CPU define 8 interrupt sources */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/loongson/common/
H A Dserial.c33 .irq = MIPS_CPU_IRQ_BASE + (int), \
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/mipssim/
H A Dsim_int.c79 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
H A Dsim_time.c76 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/emma/markeins/
H A Dirq.c304 setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade);
312 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
316 do_IRQ(MIPS_CPU_IRQ_BASE + 1);
318 do_IRQ(MIPS_CPU_IRQ_BASE + 0);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/dec/
H A Dinterrupts.h91 #define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/sgi/
H A Dip22.h28 #define SGINT_CPU MIPS_CPU_IRQ_BASE /* MIPS CPU define 8 interrupt sources */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/loongson/common/
H A Dserial.c33 .irq = MIPS_CPU_IRQ_BASE + (int), \
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/mipssim/
H A Dsim_int.c79 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
H A Dsim_time.c76 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/mach-cavium-octeon/
H A Dirq.h12 #define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/mach-pnx833x/
H A Dirq-mapping.h42 #define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-cavium-octeon/
H A Dirq.h12 #define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-pnx833x/
H A Dirq-mapping.h42 #define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/
H A Dsni.h144 #define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
152 #define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5)
177 #define PCIMT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE+6)
H A Djazz.h206 #define JAZZ_TIMER_IRQ (MIPS_CPU_IRQ_BASE+6)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/
H A Dsni.h144 #define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
152 #define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5)
177 #define PCIMT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE+6)

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