Searched hist:96422 (Results 1 - 4 of 4) sorted by relevance
| /freebsd-10.2-release/lib/libc/sparc64/sys/ | ||
| H A D | __sparc_utrap_emul.c | diff 96422 Sat May 11 21:20:05 MDT 2002 jake Add a support macro to convert the 5-bit packed register field of a floating point instruction into a 6-bit register number for double and quad arguments. Make use of the new INSFPdq_RN macro where apporpriate; this is required for correctly handling the "high" fp registers (>= %f32). Fix a number of bugs related to the handling of the high registers which were caused by using __fpu_[gs]etreg() where __fpu_[gs]etreg64() should be used (the former can only access the low, single-precision, registers). Submitted by: tmm |
| /freebsd-10.2-release/sys/sparc64/include/ | ||
| H A D | instr.h | diff 96422 Sat May 11 21:20:05 MDT 2002 jake Add a support macro to convert the 5-bit packed register field of a floating point instruction into a 6-bit register number for double and quad arguments. Make use of the new INSFPdq_RN macro where apporpriate; this is required for correctly handling the "high" fp registers (>= %f32). Fix a number of bugs related to the handling of the high registers which were caused by using __fpu_[gs]etreg() where __fpu_[gs]etreg64() should be used (the former can only access the low, single-precision, registers). Submitted by: tmm |
| /freebsd-10.2-release/lib/libc/sparc64/fpu/ | ||
| H A D | fpu.c | diff 96422 Sat May 11 21:20:05 MDT 2002 jake Add a support macro to convert the 5-bit packed register field of a floating point instruction into a 6-bit register number for double and quad arguments. Make use of the new INSFPdq_RN macro where apporpriate; this is required for correctly handling the "high" fp registers (>= %f32). Fix a number of bugs related to the handling of the high registers which were caused by using __fpu_[gs]etreg() where __fpu_[gs]etreg64() should be used (the former can only access the low, single-precision, registers). Submitted by: tmm |
| H A D | fpu_explode.c | diff 96422 Sat May 11 21:20:05 MDT 2002 jake Add a support macro to convert the 5-bit packed register field of a floating point instruction into a 6-bit register number for double and quad arguments. Make use of the new INSFPdq_RN macro where apporpriate; this is required for correctly handling the "high" fp registers (>= %f32). Fix a number of bugs related to the handling of the high registers which were caused by using __fpu_[gs]etreg() where __fpu_[gs]etreg64() should be used (the former can only access the low, single-precision, registers). Submitted by: tmm |
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