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| /freebsd-11-stable/sys/dev/aic7xxx/ | ||
| H A D | aic7xxx.c | diff 81170 Sun Aug 05 20:20:12 MDT 2001 gibbs aic7xxx.c: Correct an off by one in our critical section handling. SEQADDR always reads the next instruction to execute, so we must subtract one from its value before making comparisons with entries in the critical section table. Print a few additional registers whenever we dump card state. Show the SCB_CONTROL and SCB_TAG values for all pending SCBs in card SCB ram when dumping card state. aic7xxx.seq: Fix a bug introduced while optimizing the SDPTR path. We would ack the SDPTR message twice on Ultra2 or better chips if it occurred after all data had been transferred for a transaction. Change our workaround for the PCI2.1 retry bug on some chips. Although the previous workaround was logically correct, its faster method of draining the FIFO seemed to occassionally confuse the FIFO state. We now drain the FIFO at half the speed which avoids the problem. aic7xxx_pci.c: Chips with the PCI 2.1 retry bug can't handle a 16byte cachesize. If the cachesize is set to 16bytes, drop it to 0. |
| H A D | aic7xxx.seq | diff 81170 Sun Aug 05 20:20:12 MDT 2001 gibbs aic7xxx.c: Correct an off by one in our critical section handling. SEQADDR always reads the next instruction to execute, so we must subtract one from its value before making comparisons with entries in the critical section table. Print a few additional registers whenever we dump card state. Show the SCB_CONTROL and SCB_TAG values for all pending SCBs in card SCB ram when dumping card state. aic7xxx.seq: Fix a bug introduced while optimizing the SDPTR path. We would ack the SDPTR message twice on Ultra2 or better chips if it occurred after all data had been transferred for a transaction. Change our workaround for the PCI2.1 retry bug on some chips. Although the previous workaround was logically correct, its faster method of draining the FIFO seemed to occassionally confuse the FIFO state. We now drain the FIFO at half the speed which avoids the problem. aic7xxx_pci.c: Chips with the PCI 2.1 retry bug can't handle a 16byte cachesize. If the cachesize is set to 16bytes, drop it to 0. |
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