Searched hist:61616 (Results 1 - 6 of 6) sorted by relevance
| /freebsd-10.1-release/sys/amd64/amd64/ | ||
| H A D | initcpu.c | diff 61616 Tue Jun 13 07:10:37 MDT 2000 kato Added new options CPU_PPRO2CELERON and CPU_L2_LATENCY to support Socket 8 to 370 converters. When (1) CPU_PPRO2CELERON option is defined, (2) Intel CPU is found and (3) CPU ID is 0x66?, L2 cache is enabled through MSR 0x11e. The L2 cache latency value can be specified by CPU_L2_LATENCY option. Default value of L2 cache latency is 5. These options are useful if you use Socket 8 to Socket 370 converter (e.g. Power Leap's PL-Pro/II.) Most PentiumPro BIOSs don't enable L2 cache of Mendocino Celeron CPUs because they don't know Celeron CPUs. These options are needles if you use a Coppermine (FCPGA) Celeron or PentiumIII, becuase the L2 cache enable bit is hard wired and L2 cache is always enabled. |
| /freebsd-10.1-release/sys/i386/i386/ | ||
| H A D | initcpu.c | diff 61616 Tue Jun 13 07:10:37 MDT 2000 kato Added new options CPU_PPRO2CELERON and CPU_L2_LATENCY to support Socket 8 to 370 converters. When (1) CPU_PPRO2CELERON option is defined, (2) Intel CPU is found and (3) CPU ID is 0x66?, L2 cache is enabled through MSR 0x11e. The L2 cache latency value can be specified by CPU_L2_LATENCY option. Default value of L2 cache latency is 5. These options are useful if you use Socket 8 to Socket 370 converter (e.g. Power Leap's PL-Pro/II.) Most PentiumPro BIOSs don't enable L2 cache of Mendocino Celeron CPUs because they don't know Celeron CPUs. These options are needles if you use a Coppermine (FCPGA) Celeron or PentiumIII, becuase the L2 cache enable bit is hard wired and L2 cache is always enabled. |
| /freebsd-10.1-release/sys/conf/ | ||
| H A D | options.pc98 | diff 61616 Tue Jun 13 07:10:37 MDT 2000 kato Added new options CPU_PPRO2CELERON and CPU_L2_LATENCY to support Socket 8 to 370 converters. When (1) CPU_PPRO2CELERON option is defined, (2) Intel CPU is found and (3) CPU ID is 0x66?, L2 cache is enabled through MSR 0x11e. The L2 cache latency value can be specified by CPU_L2_LATENCY option. Default value of L2 cache latency is 5. These options are useful if you use Socket 8 to Socket 370 converter (e.g. Power Leap's PL-Pro/II.) Most PentiumPro BIOSs don't enable L2 cache of Mendocino Celeron CPUs because they don't know Celeron CPUs. These options are needles if you use a Coppermine (FCPGA) Celeron or PentiumIII, becuase the L2 cache enable bit is hard wired and L2 cache is always enabled. |
| H A D | options.i386 | diff 61616 Tue Jun 13 07:10:37 MDT 2000 kato Added new options CPU_PPRO2CELERON and CPU_L2_LATENCY to support Socket 8 to 370 converters. When (1) CPU_PPRO2CELERON option is defined, (2) Intel CPU is found and (3) CPU ID is 0x66?, L2 cache is enabled through MSR 0x11e. The L2 cache latency value can be specified by CPU_L2_LATENCY option. Default value of L2 cache latency is 5. These options are useful if you use Socket 8 to Socket 370 converter (e.g. Power Leap's PL-Pro/II.) Most PentiumPro BIOSs don't enable L2 cache of Mendocino Celeron CPUs because they don't know Celeron CPUs. These options are needles if you use a Coppermine (FCPGA) Celeron or PentiumIII, becuase the L2 cache enable bit is hard wired and L2 cache is always enabled. |
| H A D | NOTES | diff 61616 Tue Jun 13 07:10:37 MDT 2000 kato Added new options CPU_PPRO2CELERON and CPU_L2_LATENCY to support Socket 8 to 370 converters. When (1) CPU_PPRO2CELERON option is defined, (2) Intel CPU is found and (3) CPU ID is 0x66?, L2 cache is enabled through MSR 0x11e. The L2 cache latency value can be specified by CPU_L2_LATENCY option. Default value of L2 cache latency is 5. These options are useful if you use Socket 8 to Socket 370 converter (e.g. Power Leap's PL-Pro/II.) Most PentiumPro BIOSs don't enable L2 cache of Mendocino Celeron CPUs because they don't know Celeron CPUs. These options are needles if you use a Coppermine (FCPGA) Celeron or PentiumIII, becuase the L2 cache enable bit is hard wired and L2 cache is always enabled. |
| /freebsd-10.1-release/sys/i386/conf/ | ||
| H A D | NOTES | diff 61616 Tue Jun 13 07:10:37 MDT 2000 kato Added new options CPU_PPRO2CELERON and CPU_L2_LATENCY to support Socket 8 to 370 converters. When (1) CPU_PPRO2CELERON option is defined, (2) Intel CPU is found and (3) CPU ID is 0x66?, L2 cache is enabled through MSR 0x11e. The L2 cache latency value can be specified by CPU_L2_LATENCY option. Default value of L2 cache latency is 5. These options are useful if you use Socket 8 to Socket 370 converter (e.g. Power Leap's PL-Pro/II.) Most PentiumPro BIOSs don't enable L2 cache of Mendocino Celeron CPUs because they don't know Celeron CPUs. These options are needles if you use a Coppermine (FCPGA) Celeron or PentiumIII, becuase the L2 cache enable bit is hard wired and L2 cache is always enabled. |
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