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| /freebsd-10.2-release/sys/dev/aic7xxx/ | ||
| H A D | aic7xxx_93cx6.c | diff 55581 Fri Jan 07 23:08:20 MST 2000 gibbs Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ. |
| H A D | aic7xxx.c | diff 55581 Fri Jan 07 23:08:20 MST 2000 gibbs Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ. |
| H A D | aic7xxx.h | diff 55581 Fri Jan 07 23:08:20 MST 2000 gibbs Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ. |
| H A D | aic7xxx.reg | diff 55581 Fri Jan 07 23:08:20 MST 2000 gibbs Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ. |
| H A D | aic7xxx.seq | diff 55581 Fri Jan 07 23:08:20 MST 2000 gibbs Update copyrights to Y2K. 93cx6.c: Make the SRAM dump output a little prettier. aic7xxx.c: Store all SG entries into our SG array in kernel space. This makes data-overrun and other error reporting more useful as we can dump all SG entries. In the past, we only stored the SG entries that the sequencer might need to access, which meant we skipped the first element that is embedded into the SCB. Add a table of chip strings and replace ugly switch statements with table lookups. Add a table with bus phase strings and message reponses to parity errors in those phases. Use the table to pretty print bus phase messages as well as collapse another switch statement. Fix a bug in target mode that could cause us to unpause the sequencer early in bus reset processing. Add the 80MHz/DT mode into our syncrate table. This rate is not yet used or enabled. Correct some comments, clean up some code... aic7xxx.h: Add U160 controller feature information. Add some more bit fields for various SEEPROM formats. aic7xxx.reg: Add U160 register and register bit definitions. aic7xxx.seq: Make phasemis state tracking more straight forward. This avoids the consumption of SINDEX which is a very useful register. For the U160 chips, you must use the 'mov' instruction to update DFCNTRL. Using 'or' to set the PRELOADED bit is completely ineffective. At the end of the command phase, wair for our ACK signal to de-assert before disabling the SCSI dma engine. For slow devices, this avoids clearing the ACK before the other end has had a chance to see it and lower REQ. |
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