Searched hist:34021 (Results 1 - 11 of 11) sorted by relevance
| /freebsd-10.2-release/sys/x86/isa/ | ||
| H A D | nmi.c | diff 34021 Tue Mar 03 22:56:30 MST 1998 tegge When entering the apic version of slow interrupt handler, level interrupts are masked, and EOI is sent iff the corresponding ISR bit is set in the local apic. If the CPU cannot obtain the interrupt service lock (currently the global kernel lock) the interrupt is forwarded to the CPU holding that lock. Clock interrupts now have higher priority than other slow interrupts. |
| /freebsd-10.2-release/sys/i386/include/ | ||
| H A D | smp.h | diff 34021 Tue Mar 03 22:56:30 MST 1998 tegge When entering the apic version of slow interrupt handler, level interrupts are masked, and EOI is sent iff the corresponding ISR bit is set in the local apic. If the CPU cannot obtain the interrupt service lock (currently the global kernel lock) the interrupt is forwarded to the CPU holding that lock. Clock interrupts now have higher priority than other slow interrupts. |
| /freebsd-10.2-release/sys/sys/ | ||
| H A D | smp.h | diff 34021 Tue Mar 03 22:56:30 MST 1998 tegge When entering the apic version of slow interrupt handler, level interrupts are masked, and EOI is sent iff the corresponding ISR bit is set in the local apic. If the CPU cannot obtain the interrupt service lock (currently the global kernel lock) the interrupt is forwarded to the CPU holding that lock. Clock interrupts now have higher priority than other slow interrupts. |
| /freebsd-10.2-release/sys/amd64/include/ | ||
| H A D | smp.h | diff 34021 Tue Mar 03 22:56:30 MST 1998 tegge When entering the apic version of slow interrupt handler, level interrupts are masked, and EOI is sent iff the corresponding ISR bit is set in the local apic. If the CPU cannot obtain the interrupt service lock (currently the global kernel lock) the interrupt is forwarded to the CPU holding that lock. Clock interrupts now have higher priority than other slow interrupts. |
| /freebsd-10.2-release/sys/i386/i386/ | ||
| H A D | apic_vector.s | diff 34021 Tue Mar 03 22:56:30 MST 1998 tegge When entering the apic version of slow interrupt handler, level interrupts are masked, and EOI is sent iff the corresponding ISR bit is set in the local apic. If the CPU cannot obtain the interrupt service lock (currently the global kernel lock) the interrupt is forwarded to the CPU holding that lock. Clock interrupts now have higher priority than other slow interrupts. |
| H A D | mp_machdep.c | diff 34021 Tue Mar 03 22:56:30 MST 1998 tegge When entering the apic version of slow interrupt handler, level interrupts are masked, and EOI is sent iff the corresponding ISR bit is set in the local apic. If the CPU cannot obtain the interrupt service lock (currently the global kernel lock) the interrupt is forwarded to the CPU holding that lock. Clock interrupts now have higher priority than other slow interrupts. |
| /freebsd-10.2-release/sys/amd64/amd64/ | ||
| H A D | apic_vector.S | diff 34021 Tue Mar 03 22:56:30 MST 1998 tegge When entering the apic version of slow interrupt handler, level interrupts are masked, and EOI is sent iff the corresponding ISR bit is set in the local apic. If the CPU cannot obtain the interrupt service lock (currently the global kernel lock) the interrupt is forwarded to the CPU holding that lock. Clock interrupts now have higher priority than other slow interrupts. |
| H A D | mp_machdep.c | diff 34021 Tue Mar 03 22:56:30 MST 1998 tegge When entering the apic version of slow interrupt handler, level interrupts are masked, and EOI is sent iff the corresponding ISR bit is set in the local apic. If the CPU cannot obtain the interrupt service lock (currently the global kernel lock) the interrupt is forwarded to the CPU holding that lock. Clock interrupts now have higher priority than other slow interrupts. |
| /freebsd-10.2-release/sys/kern/ | ||
| H A D | subr_smp.c | diff 34021 Tue Mar 03 22:56:30 MST 1998 tegge When entering the apic version of slow interrupt handler, level interrupts are masked, and EOI is sent iff the corresponding ISR bit is set in the local apic. If the CPU cannot obtain the interrupt service lock (currently the global kernel lock) the interrupt is forwarded to the CPU holding that lock. Clock interrupts now have higher priority than other slow interrupts. |
| /freebsd-10.2-release/sys/x86/include/ | ||
| H A D | mptable.h | diff 34021 Tue Mar 03 22:56:30 MST 1998 tegge When entering the apic version of slow interrupt handler, level interrupts are masked, and EOI is sent iff the corresponding ISR bit is set in the local apic. If the CPU cannot obtain the interrupt service lock (currently the global kernel lock) the interrupt is forwarded to the CPU holding that lock. Clock interrupts now have higher priority than other slow interrupts. |
| /freebsd-10.2-release/sys/x86/x86/ | ||
| H A D | mptable.c | diff 34021 Tue Mar 03 22:56:30 MST 1998 tegge When entering the apic version of slow interrupt handler, level interrupts are masked, and EOI is sent iff the corresponding ISR bit is set in the local apic. If the CPU cannot obtain the interrupt service lock (currently the global kernel lock) the interrupt is forwarded to the CPU holding that lock. Clock interrupts now have higher priority than other slow interrupts. |
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