Searched hist:282867 (Results 1 - 3 of 3) sorted by relevance
| /freebsd-11-stable/sys/arm64/arm64/ | ||
| H A D | locore.S | diff 282867 Wed May 13 17:04:44 MDT 2015 zbb Add support for ARM GICv3 interrupt controller used in some ARM64 chips GICv3 allows to distribute interrupts to more than 8 cores served by the previous GIC revisions. GICv3 introduces additional logic in form of Re-Distributors associated with particular CPUs to determine the highest priority interrupts and manage PPIs and LPIs (Locality-specific Peripheral Interrupts). Interrupts routing is based on CPUs' affinity numbers. CPU interface was changed to be accessible via CPU System Registers and this is the preferred (and supported) method in this driver. Obtained from: Semihalf Reviewed by: andrew, emaste, ian, imp Sponsored by: The FreeBSD Foundation |
| /freebsd-11-stable/sys/arm64/include/ | ||
| H A D | armreg.h | diff 282867 Wed May 13 17:04:44 MDT 2015 zbb Add support for ARM GICv3 interrupt controller used in some ARM64 chips GICv3 allows to distribute interrupts to more than 8 cores served by the previous GIC revisions. GICv3 introduces additional logic in form of Re-Distributors associated with particular CPUs to determine the highest priority interrupts and manage PPIs and LPIs (Locality-specific Peripheral Interrupts). Interrupts routing is based on CPUs' affinity numbers. CPU interface was changed to be accessible via CPU System Registers and this is the preferred (and supported) method in this driver. Obtained from: Semihalf Reviewed by: andrew, emaste, ian, imp Sponsored by: The FreeBSD Foundation |
| /freebsd-11-stable/sys/conf/ | ||
| H A D | files.arm64 | diff 282867 Wed May 13 17:04:44 MDT 2015 zbb Add support for ARM GICv3 interrupt controller used in some ARM64 chips GICv3 allows to distribute interrupts to more than 8 cores served by the previous GIC revisions. GICv3 introduces additional logic in form of Re-Distributors associated with particular CPUs to determine the highest priority interrupts and manage PPIs and LPIs (Locality-specific Peripheral Interrupts). Interrupts routing is based on CPUs' affinity numbers. CPU interface was changed to be accessible via CPU System Registers and this is the preferred (and supported) method in this driver. Obtained from: Semihalf Reviewed by: andrew, emaste, ian, imp Sponsored by: The FreeBSD Foundation |
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