Searched hist:281438 (Results 1 - 10 of 10) sorted by relevance
| /freebsd-11-stable/sys/arm/samsung/exynos/ | ||
| H A D | exynos_uart.c | diff 281438 Sat Apr 11 15:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| /freebsd-11-stable/sys/dev/uart/ | ||
| H A D | uart_dev_lpc.c | diff 281438 Sat Apr 11 15:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_dev_pl011.c | diff 281438 Sat Apr 11 15:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_cpu_fdt.c | diff 281438 Sat Apr 11 15:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_bus_fdt.c | diff 281438 Sat Apr 11 15:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_cpu.h | diff 281438 Sat Apr 11 15:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_bus.h | diff 281438 Sat Apr 11 15:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_dev_ns8250.c | diff 281438 Sat Apr 11 15:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| H A D | uart_core.c | diff 281438 Sat Apr 11 15:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
| /freebsd-11-stable/sys/sparc64/pci/ | ||
| H A D | sbbc.c | diff 281438 Sat Apr 11 15:23:03 MDT 2015 andrew Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
Completed in 359 milliseconds