Searched hist:230641 (Results 1 - 5 of 5) sorted by relevance
/freebsd-11-stable/sys/dev/ichiic/ | ||
H A D | ig4_acpi.c | diff 339030 Sun Sep 30 23:19:58 MDT 2018 gonzo MFC r338111, r338215 r338111: [ig4] add ACPI Device HID for AMD platforms Added ACPI Device HID AMDI0010 for the designware I2C controllers in future AMD platforms. Also, when verifying component version check for minimal value instead of exact match. PR: 230641 Submitted by: Rajesh <rajfbsd@gmail.com> Reviewed by: cem, gonzo Differential Revision: https://reviews.freebsd.org/D16670 r338215: [ig4] Fix I/O timeout issue with Designware I2C controller on AMD platforms Due to hardware limitation AMD I2C controller can't trigger pending interrupt if interrupt status has been changed after clearing interrupt status bits. So, I2C will lose the interrupt and IO will be timed out. Implements a workaround to disable I2C controller interrupt and re-enable I2C interrupt before existing interrupt handler. Submitted by: rajfbsd@gmail.com Differential Revision: https://reviews.freebsd.org/D16720 |
H A D | ig4_reg.h | diff 339030 Sun Sep 30 23:19:58 MDT 2018 gonzo MFC r338111, r338215 r338111: [ig4] add ACPI Device HID for AMD platforms Added ACPI Device HID AMDI0010 for the designware I2C controllers in future AMD platforms. Also, when verifying component version check for minimal value instead of exact match. PR: 230641 Submitted by: Rajesh <rajfbsd@gmail.com> Reviewed by: cem, gonzo Differential Revision: https://reviews.freebsd.org/D16670 r338215: [ig4] Fix I/O timeout issue with Designware I2C controller on AMD platforms Due to hardware limitation AMD I2C controller can't trigger pending interrupt if interrupt status has been changed after clearing interrupt status bits. So, I2C will lose the interrupt and IO will be timed out. Implements a workaround to disable I2C controller interrupt and re-enable I2C interrupt before existing interrupt handler. Submitted by: rajfbsd@gmail.com Differential Revision: https://reviews.freebsd.org/D16720 |
H A D | ig4_var.h | diff 339030 Sun Sep 30 23:19:58 MDT 2018 gonzo MFC r338111, r338215 r338111: [ig4] add ACPI Device HID for AMD platforms Added ACPI Device HID AMDI0010 for the designware I2C controllers in future AMD platforms. Also, when verifying component version check for minimal value instead of exact match. PR: 230641 Submitted by: Rajesh <rajfbsd@gmail.com> Reviewed by: cem, gonzo Differential Revision: https://reviews.freebsd.org/D16670 r338215: [ig4] Fix I/O timeout issue with Designware I2C controller on AMD platforms Due to hardware limitation AMD I2C controller can't trigger pending interrupt if interrupt status has been changed after clearing interrupt status bits. So, I2C will lose the interrupt and IO will be timed out. Implements a workaround to disable I2C controller interrupt and re-enable I2C interrupt before existing interrupt handler. Submitted by: rajfbsd@gmail.com Differential Revision: https://reviews.freebsd.org/D16720 |
H A D | ig4_iic.c | diff 339030 Sun Sep 30 23:19:58 MDT 2018 gonzo MFC r338111, r338215 r338111: [ig4] add ACPI Device HID for AMD platforms Added ACPI Device HID AMDI0010 for the designware I2C controllers in future AMD platforms. Also, when verifying component version check for minimal value instead of exact match. PR: 230641 Submitted by: Rajesh <rajfbsd@gmail.com> Reviewed by: cem, gonzo Differential Revision: https://reviews.freebsd.org/D16670 r338215: [ig4] Fix I/O timeout issue with Designware I2C controller on AMD platforms Due to hardware limitation AMD I2C controller can't trigger pending interrupt if interrupt status has been changed after clearing interrupt status bits. So, I2C will lose the interrupt and IO will be timed out. Implements a workaround to disable I2C controller interrupt and re-enable I2C interrupt before existing interrupt handler. Submitted by: rajfbsd@gmail.com Differential Revision: https://reviews.freebsd.org/D16720 |
/freebsd-11-stable/sys/dev/sound/pci/hda/ | ||
H A D | hdaa.c | diff 230641 Sat Jan 28 07:37:53 MST 2012 mav Fix HBR enabling condition. cchs is from 0 to 7, not from 1 to 8. |
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