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| H A D | if_axereg.h | diff 226743 Tue Oct 25 18:42:16 MDT 2011 yongari Implement TX/RX checksum offloading support for ASIX AX88772B controller. AX88772B data sheet does not show detailed information about checksum offloading related things. It seems the controller has lots of options to support checksum offloading but I failed to understand why this feature requires so much complex controller configuration and status bits. One of major difference between AX88772B and its predecessor is AX88772B uses a new RX header format when RX checksum offloading is enabled. It also requires the received length of a frame should be multiple of 4. Controller will pad necessary bytes to make the length of received frame to be multiple of 4. It is driver's responsibility to offset this pad bytes. Note, AX88772B could be configured to get partial checksum value in in RX header. This mode uses different RX header format and currently we don't use that fature. This change makes axe(4) use driver specific MII attach handler to override uether(9)'s default MII attach and announce flow-control capability for AX88178/AX88772A/AX88772B to PHY drivers. It seems original AX88772 also supports flow-control but I didn't enable it due to lack of test/access to the controller. The flow-control threshold parameter is loaded from EEPROM and there is no way to override this value without reprogramming EEPROM. For AX88772B, TX/RX IP/TCP/UDP checksum offloading is announced to network stack. IPv6 and PPPoE checksum offloading is also supported by controller but we have no way to take advantage of these features. Driver already knows PHY address so make PHY driver know that information and remove unnecessary PHY address check used in miibus_readreg/miibus_writereg callbacks. Also announce AX88178, AX88772A and AX88772B support VLAN over-sized frame. While I'm here clean up headers and remove axe_start() in axe_init() because the link wouldn't be available right after media change. |
| H A D | if_axe.c | diff 226743 Tue Oct 25 18:42:16 MDT 2011 yongari Implement TX/RX checksum offloading support for ASIX AX88772B controller. AX88772B data sheet does not show detailed information about checksum offloading related things. It seems the controller has lots of options to support checksum offloading but I failed to understand why this feature requires so much complex controller configuration and status bits. One of major difference between AX88772B and its predecessor is AX88772B uses a new RX header format when RX checksum offloading is enabled. It also requires the received length of a frame should be multiple of 4. Controller will pad necessary bytes to make the length of received frame to be multiple of 4. It is driver's responsibility to offset this pad bytes. Note, AX88772B could be configured to get partial checksum value in in RX header. This mode uses different RX header format and currently we don't use that fature. This change makes axe(4) use driver specific MII attach handler to override uether(9)'s default MII attach and announce flow-control capability for AX88178/AX88772A/AX88772B to PHY drivers. It seems original AX88772 also supports flow-control but I didn't enable it due to lack of test/access to the controller. The flow-control threshold parameter is loaded from EEPROM and there is no way to override this value without reprogramming EEPROM. For AX88772B, TX/RX IP/TCP/UDP checksum offloading is announced to network stack. IPv6 and PPPoE checksum offloading is also supported by controller but we have no way to take advantage of these features. Driver already knows PHY address so make PHY driver know that information and remove unnecessary PHY address check used in miibus_readreg/miibus_writereg callbacks. Also announce AX88178, AX88772A and AX88772B support VLAN over-sized frame. While I'm here clean up headers and remove axe_start() in axe_init() because the link wouldn't be available right after media change. |
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