Searched hist:205364 (Results 1 - 5 of 5) sorted by relevance
| /freebsd-11.0-release/sys/mips/sibyte/ | ||
| H A D | sb_scd.h | diff 205364 Sat Mar 20 06:05:21 MDT 2010 neel Sibyte provides a 64-bit read-only counter that counts at half the processor frequency. This counter can be accessed coherently from both cores. Use this as the preferred timecounter for the SWARM kernels. The CP0 COUNT register is unusable as the timecounter on SMP platforms because the COUNT registers on different CPUs are not guaranteed to be in sync. |
| H A D | sb_scd.c | diff 205364 Sat Mar 20 06:05:21 MDT 2010 neel Sibyte provides a 64-bit read-only counter that counts at half the processor frequency. This counter can be accessed coherently from both cores. Use this as the preferred timecounter for the SWARM kernels. The CP0 COUNT register is unusable as the timecounter on SMP platforms because the COUNT registers on different CPUs are not guaranteed to be in sync. |
| H A D | sb_machdep.c | diff 205364 Sat Mar 20 06:05:21 MDT 2010 neel Sibyte provides a 64-bit read-only counter that counts at half the processor frequency. This counter can be accessed coherently from both cores. Use this as the preferred timecounter for the SWARM kernels. The CP0 COUNT register is unusable as the timecounter on SMP platforms because the COUNT registers on different CPUs are not guaranteed to be in sync. |
| /freebsd-11.0-release/sys/mips/include/ | ||
| H A D | clock.h | diff 205364 Sat Mar 20 06:05:21 MDT 2010 neel Sibyte provides a 64-bit read-only counter that counts at half the processor frequency. This counter can be accessed coherently from both cores. Use this as the preferred timecounter for the SWARM kernels. The CP0 COUNT register is unusable as the timecounter on SMP platforms because the COUNT registers on different CPUs are not guaranteed to be in sync. |
| /freebsd-11.0-release/sys/mips/mips/ | ||
| H A D | tick.c | diff 205364 Sat Mar 20 06:05:21 MDT 2010 neel Sibyte provides a 64-bit read-only counter that counts at half the processor frequency. This counter can be accessed coherently from both cores. Use this as the preferred timecounter for the SWARM kernels. The CP0 COUNT register is unusable as the timecounter on SMP platforms because the COUNT registers on different CPUs are not guaranteed to be in sync. |
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