Searched hist:1040 (Results 1 - 25 of 44) sorted by relevance
/freebsd-10.2-release/gnu/usr.bin/ | ||
H A D | Makefile.inc | 1040 Sun Jan 30 00:31:51 MST 1994 rgrimes New files for relocated source code. |
/freebsd-10.2-release/share/man/man4/ | ||
H A D | isp.4 | diff 113772 Sun Apr 20 22:10:13 MDT 2003 obrien Note the Qlogic 1040 is a KZPBA in DEC-speak. Reviewed by: wilko |
/freebsd-10.2-release/sys/dev/isp/ | ||
H A D | isp_target.h | diff 73319 Fri Mar 02 06:28:55 MST 2001 mjacob Switch to using 16 bit handles instead of 32 bit handles. This is a pretty invasive change, but there are three good reasons to do this: 1. We'll never have > 16 bits of handle. 2. We can (eventually) enable the RIO (Reduced Interrupt Operation) bits which return multiple completing 16 bit handles in mailbox registers. 3. The !)$*)$*~)@$*~)$* Qlogic target mode for parallel SCSI spec changed such that at_reserved (which was 32 bits) was split into two pieces- and one of which was a 16 bit handle id that functions like the at_rxid for Fibre Channel (a tag for the f/w to correlate CTIOs with a particular command). Since we had to muck with that and this changed the whole handler architecture, we might as well... Propagate new at_handle on through int ct_fwhandle. Follow implications of changing to 16 bit handles. These above changes at least get Qlogic 1040 cards working in target mode again. 1080/12160 cards don't work yet. In isp.c: Prepare for doing all loop management in outer layers. |
H A D | isp.c | diff 73319 Fri Mar 02 06:28:55 MST 2001 mjacob Switch to using 16 bit handles instead of 32 bit handles. This is a pretty invasive change, but there are three good reasons to do this: 1. We'll never have > 16 bits of handle. 2. We can (eventually) enable the RIO (Reduced Interrupt Operation) bits which return multiple completing 16 bit handles in mailbox registers. 3. The !)$*)$*~)@$*~)$* Qlogic target mode for parallel SCSI spec changed such that at_reserved (which was 32 bits) was split into two pieces- and one of which was a 16 bit handle id that functions like the at_rxid for Fibre Channel (a tag for the f/w to correlate CTIOs with a particular command). Since we had to muck with that and this changed the whole handler architecture, we might as well... Propagate new at_handle on through int ct_fwhandle. Follow implications of changing to 16 bit handles. These above changes at least get Qlogic 1040 cards working in target mode again. 1080/12160 cards don't work yet. In isp.c: Prepare for doing all loop management in outer layers. diff 64095 Tue Aug 01 06:51:05 MDT 2000 mjacob Major whacking for core version 2.0. A major motivator for 2.0 and these changes is that there's now a Solaris port of this driver, so some things in the core version had to change (not much, but some). In order, from the top.....: A lot of error strings are gathered in one place at the head of the file. This caused me to rewrite them to look consistent (with respect to things like 'Port 0x%' and 'Target %d' and 'Loop ID 0x%x'. The major mailbox function, isp_mboxcmd, now takes a third argument, which is a mask that selectively says whether mailbox command failures will be logged. This will substantially reduce a lot of spurious noise from the driver. At the first run through isp_reset we used to try and get the current running firmware's revision by issuing a mailbox command. This would invariably fail on alpha's with anything but a Qlogic 1040 since SRM doesn't *start* the f/w on these cards. Instead, we now see whether we're sitting ROM state before trying to get a running BIOS loaded f/w version. All CFGPRINTF/PRINTF/IDPRINTF macros have been replaced with calls to isp_prt. There are seperate print levels that can be independently set (see ispvar.h), which include debugging, etc. All SYS_DELAY macros are now USEC_DELAY macros. RQUEST_QUEUE_LEN and RESULT_QUEUE_LEN now take ispsoftc as a parameter- the Fibre Channel cards and the Ultra2/Ultra3 cards can have 16 bit request queue entry indices, so we can make a 1024 entry index for them instead of the 256 entries we've had until now. A major change it to fix isp_fclink_test to actually only wait the delay of time specified in the microsecond argument being passed. The problem has always been that a call to isp_mboxcmd to get he current firmware state takes an unknown (sometimes long) amount of time- this is if the firmware is busy doing PLOGIs while we ask it what's up. So, up until now, the usdelay argument has been a joke. The net effect has been that if you boot without being plugged into a good loop or into a switch, you hang. Massively annonying, and hard to fix because the actual time delta was impossible to know from just guessing. Now, using the new GET_NANOTIME macros, a precise and measured amount of USEC_DELAY calls are done so that only the specified usecdelay is allowed to pass. This means that if the initial startup of the firmware if followed by a call from isp_freebsd.c:isp_attach to isp_control(isp, ISP_FCLINK_TEST, &tdelay) where tdelay is 2 * 1000000, no more than two seconds will actually elapse before we leave concluding that the cable is unhooked. Jeez. About time.... Change the ispscsicmd entry point to isp_start, and the XS_CMD_DONE macro to a call to the platform supplied isp_done (sane naming). Limit our size of request queue completions we'll look at at interrupt time. Since we've increased the size of the Request Queue (and the size of the Response Queue proportionally), let's not create an interrupt stack overflow by having to keep a max completion list (forw links are not an option because this is common code with some platforms that don't have link space in their XS_T structures). A limit of 32 is not unreasonable- I doubt there'd be even this many request queue completions at a time- remember, most boards now use fast posting for normal command completion instead of filling out response queue entries. In the isp_mboxcmd cleanup, also create an array of command names so that "ABOUT FIRMWARE" can be printed instead of "CMD #8". Remove the isp_lostcmd function- it's been deprecated for a while. Remove isp_dumpregs- the ISP_DUMPREGS goes to the specific bus register dump fucntion. Various other cleanups. diff 62174 Tue Jun 27 19:44:31 MDT 2000 mjacob Fix usage of DELAY (SYS_DELAY is the platform independent local define). Fix stupidity wrt checking whether we've gone to LOOP_PDB_RCVD loopstate- it's okay to be greater than this state. D'oh! Protect calls to isp_pdb_sync and isp_fclink_state with IS_FC macros. Completely redo mailbox command routine (in preparation to make this possibly wait rather than poll for completion). Make a major attempt to solve the 'lost interrupt' problem 1. Problem The Qlogic cards would appear to 'lose' interrupts, i.e., a legitimate regular SCSI command placed on the request queue would never complete and the watchdog routine in the driver would eventually wakeup and catch it. This would typically only happen on Alphas, although a couple folks with 700MHz Intel platforms have also seen this. For a long time I thought it was a foulup with f/w negotiations of SYNC and/or WIDE as it always seemed to happen right after the platform it was running on had done a SET TARGET PARAMETERS mailbox command to (re)enable sync && wide (after initially forcing ASYNC/NARROW at startup). However, occasionally, the same thing would also occur for the Fibre Channel cards as well (which, ahem, have no SET TARGET PARAMETERS for transfer mode). After finally putting in a better set of watchdog routines for the platforms for this driver, it seemed to be the case that the command in question (usually a READ CAPACITY) just had up and died- the watchdog routine would catch it after ~10 seconds. For some platforms (NetBSD/OpenBSD)- an ABORT COMMAND mailbox command was sent (which would always fail- indicating that the f/w denied knowledge of this command, i.e., the f/w thought it was a done command). In any case, retrying the command worked. But this whole problem needed to be really fixed. 2. A False Step That Went in The Right Direction The mailbox code was completely rewritten to no longer try and grab the mailbox semaphore register and to try and 'by hand' complete async fast posting completions. It was also rewritten to now have separate in && out bitpatterns for registers to load to start and retrieve to complete. This means that isp_intr now handles mailbox completions. This substantially simplifies the mailbox handling code, and carries things 90% toward getting this to be a non-polled routine for this driver. This did not solve the problem, though. 3. Register Debouncing I saw some comments in some errata sheets and some notes in a Qlogic produced Linux driver (for the Qlogic 2100) that seemed to indicate that debouncing of reads of the mailbox registers might be needed, so I added this. This did not affect the problem. In fact, it made the problem worse for non-2100 cards. 5. Interrupt masking/unmasking The driver *used* to do a substantial amount of masking/unmasking of the interrupt control register. This was done to make sure that the core common code could just assume it would never get pre-empted. This apparently substantially contributed to the lost interrupt problem. The rewrite of the ICR (Interrupt Control Register), which is a separate register from the ISR (Interrupt Status Register) should not have caused any change to interrupt assertions pending. The manual does not state that it will, and the register layout seems to imply that the ICR is just an active route gate. We only enable PCI Interrupts and RISC Interrupts- this should mean that when the f/w asserts a RISC interrupt and (and the ICR allows RISC Interrupts) and we have PCI Interrupts enabled, we should get a PCI interrupt. Apparently this is a latch- not a signal route. Removing this got rid of *most* but not all, lost interrupts. 5. Watchdog Smartening I made sure that the watchdog routine would catch cases where the Qlogic's ISR showed an interrupt assertion. The watchdog routine now calls the interrupt service routine if it sees this. Some additional internal state flags were added so that the watchdog routine could then know whether the command it was in the middle of burying (because we had time it out) was in fact completed by the interrupt service routine. 6. Occasional Constipation Of Commands.. In running some very strenous high IOPs tests (generating about 11000 interrupts/second across one Qlogic 1040, one Qlogic 1080 and one Qlogic 2200 on an Alpha PC164), I found that I would get occasional but regular 'watchdog timeouts' on both the 1080 and the 2100 cards. This is under FreeBSD, and the watchdog timeout routine just marks the command in error and retries it. Invariably, right after this 'watchdog timeout' error, I'd get a command completion for the command that I had thought timed out. That is, I'd get a command completion, but the handle returned by the firmware mapped to no current command. The frequency of this problem is low under such a load- it would usually take an 30 minutes per 'lost' interrupt. I doubled the timeout for commands to see if it just was an edge case of waiting too short a period. This has no effect. I gathered and printed out microtimes for the watchdog completed command and the completion that couldn't find a command- it was always the case that the order of occurrence was "timeout, completion" separated by a time on the order of 100 to 150 ms. This caused me to consider 'firmware constipation' as to be a possible culprit. That is, resubmission of a command to the device that had suffered a watchdog timeout seemed to cause the presumed dead command to show back up. I added code in the watchdog routine that, when first entered for the command, marks the command with a flag, reissues a local timeout call for one second later, but also then issues a MARKER Request Queue entry to the Qlogic f/w. A MARKER entry is used typically after a Bus Reset to cause the f/w to get synchronized with respect to either a Bus, a Nexus or a Target. Since I've added this code, I always now see the occasional watchdog timeout, but the command that was about to be terminated always now seems to be completed after the MARKER entry is issued (and before the timeout extension fires, which would come back and *really* terminate the command). diff 45287 Sun Apr 04 03:28:29 MDT 1999 mjacob Make firmware revision a triple. Clean up some FC init stuff for board versions with no BIOS. Separate mailbox interrupts from IOCB interrupts. Read OUTMAILBOX5 while RISC_INT is active- not after you clear it (potential race condition). Clear out older broken BIG_ENDIAN goop. Don't negotiate narrow/async for LVD busses at startup if already in LVD mode. Note usage of presumptive 1040C revision. For all the LIP, PDB Changed, Loop UP/DOWN async events, mark fw state as unknown as well as marking the need to do a getpdb on targets- after a LIP for certain the f/w has to do PRLI/PLOGI for all targets again and marking f/w state as unknown gives us a fighting chance to (start to) hold up for that to complete. diff 42462 Sun Jan 10 02:55:10 MST 1999 mjacob Add some prototype deadchip detection. Set FIFO bursting (1XX0 only- it's already on for the 2XX0) and detect the broken 1040A FIFO. Change bzero to MEMZERO (portability with **nux). Use memcpy for same reason. Finally detect QUEUE FULL conditions and return this as an error that will get cam_periph_error to do it's 'tagged openings now XXX' dance. |
H A D | isp_target.c | diff 73319 Fri Mar 02 06:28:55 MST 2001 mjacob Switch to using 16 bit handles instead of 32 bit handles. This is a pretty invasive change, but there are three good reasons to do this: 1. We'll never have > 16 bits of handle. 2. We can (eventually) enable the RIO (Reduced Interrupt Operation) bits which return multiple completing 16 bit handles in mailbox registers. 3. The !)$*)$*~)@$*~)$* Qlogic target mode for parallel SCSI spec changed such that at_reserved (which was 32 bits) was split into two pieces- and one of which was a 16 bit handle id that functions like the at_rxid for Fibre Channel (a tag for the f/w to correlate CTIOs with a particular command). Since we had to muck with that and this changed the whole handler architecture, we might as well... Propagate new at_handle on through int ct_fwhandle. Follow implications of changing to 16 bit handles. These above changes at least get Qlogic 1040 cards working in target mode again. 1080/12160 cards don't work yet. In isp.c: Prepare for doing all loop management in outer layers. |
/freebsd-10.2-release/sys/mips/include/ | ||
H A D | _align.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | cache.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | cpuinfo.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | endian.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | kdb.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | _bus.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | _types.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | asm.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | atomic.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | bus.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | cache_mipsNN.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | cpu.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | cpufunc.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | cpuregs.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | db_machdep.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | elf.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | float.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | hwfunc.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | intr_machdep.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
H A D | locore.h | diff 202031 Sun Jan 10 19:52:02 MST 2010 imp Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines Get the sense of this right. We use uintpr_t for bus_addr_t when we're building everything except octeon && 32-bit. As note before, we need a clearner way, but at least now the hack is right. r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines Add in Cavium's CID. Report what the unknown CID is. r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON. Spell ld script name right. r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines Another kludge for 64-bit bus_addr_t with 32-bit pointers... r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines - Add cpu_init_interrupts function that is supposed to prepeare stuff required for spinning out interrupts later - Add API for managing intrcnt/intrnames arrays - Some minor style(9) fixes r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines For XLR adds extern for its bus space routines r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines Add some newer MIPS CO cores. r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines db_expr_t is really closer to a register_t. Submitted by: bde@ r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines - Remove bunch of declared but not defined cach-related variables - Add mips_picache_linesize and mips_pdcache_linesize variables r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines Get rid of the hardcoded constants to define cacheable memory: SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE Instead we now keep a copy of the memory regions enumerated by platform-specific code and use that to determine whether an address is cacheable or not. r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines - Commit missing part of "bt" fix: store PC register in pcb_context struct in cpu_switch and use it in stack_trace function later. pcb_regs contains state of the process stored by exception handler and therefor is not valid for sleeping processes. r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines Undo spamage of last MFC. r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines _ALIGN has to return u_long, since pointers don't fit into u_int in 64-bit mips. r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. Context info could be obtained from other sources (see below) no only from td_pcb field - Do not show a0..a3 values unless they're obtained from the stack. These are only confirmed values. - Fix bt command in DDB. Previous implementation used thread's trapframe structure as a source info for trace unwinding, but this structure is filled only when exception occurs. Valid register values for sleeping processes are in pcb_context array. For curthread use pc/sp/ra for current frame r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines - Get rid of label_t. It came from NetBSD and was used only in one place r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines - Move stack tracing function to db_trace.c - Axe unused extern MipsXXX declarations - Move all declarations for functions in exceptions.S/swtch.S from trap.c to respective headers r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines - Sync caches properly when dealing with sf_buf r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines (u_int) is the wrong type here. Use unsigned long instead, even though that's only less wrong... r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines Use unsigned long instead of unsigned for the integer casts here. The former works for both ILP32 and LP64 programming models, while the latter fails LP64. r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines - Make i/d cache size field 32-bit to prevent overflow Submited by: Neelkanth Natu r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines fix prototype for MipsEmulateBranch. r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines Better definitions for a few types for n32/n64. r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines Fixed aligned macros... r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines - Port busdma code from FreeBSD/arm. This is more mature version that takes into account all limitation to DMA memory (boundaries, alignment) and implements bounce pages. - Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines Fix atomic_store_64 prototype for 64-bit systems. r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines The MCOUNT macro isn't going to work in 64-bit mode. Add a note to this effect. r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines Provide a macro for PTR_ADDU as well. We may need to implement this differently for N32... Use PTR_ADDU in DO_AST macro. r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines Change the addu here to daddu. addu paranoina prodded by: jmallet@ r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines addu and subu are special. We need to use daddu and dsubu here to get proper behavior. Submitted by: jmallet@ r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines The SB1 has cohernet memory, so add it. Also, Maxmem is better as a long. Submitted by: Neelkanth Natu r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines compute the areas to save registers in for 64-bit access correctly. r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines First cut at 64-bit types. not 100% sure these are all correct for N32 ABI. r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines Trim unreferenced goo. SDRAM likely should be next, but it is still referenced. r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines First cut at atomics for 64-bit machines and SMP machines. # Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines Bring in cdefs.h from NetBSD to define ABI goo. Obtained from: NetBSD r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA, ala sgi, and use it in preference to a bare 'la' so that it gets translated to a 'dla' for the 64-bit pointer ABIs. r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines Use uintptr_t rather than unsigned here for 64-bit correctness. r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe this is correct. While registers are 64-bit, n32 is a 32-bit ABI and lives in a 32-bit world (with explicit 64-bit registers, however). Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4 + SZREG' to reflect the actual offset of the structure in question. r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines (1) Use uintptr_t in preference to unsigned. The latter isn't right for 64-bit case, while the former is. (2) include a SB1 specific coherency mapping Submitted by: Neelkanth Nath (2) r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines db_expr_t should be a intptr_t, not an int. These expressions can be addresses or numbers, and that's a intptr_t if I ever saw one. r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines Define COP0_SYNC for SB1 CPU. Submitted by: Neelkanth Natu r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines Switch to ABI agnostic ta0-ta3. Provide defs for this in the right places. Provide n32/n64 register name defintions. This should have no effect for the O32 builds that everybody else uses, but should help make N64 builds possible (lots of other changes are needed for that). Obtained from: NetBSD (for the regdef.h changes) r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines - Add support for handling TLS area address in kernel space. From the userland point of view get/set operations are performed using sysarch(2) call. r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines - Add guards to ensure that these files are included only once r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines - Mark temp variable as "earlyclobber" in assembler inline in atomic_fetchadd_32. Without it gcc would use it as input register for v and sometimes generate following code for function call like atomic_fetchadd_32(&(fp)->f_count, -1): 801238b4: 2402ffff li v0,-1 801238b8: c2230018 ll v1,24(s1) 801238bc: 00431021 addu v0,v0,v1 801238c0: e2220018 sc v0,24(s1) 801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8> 801238c8: 00000000 nop Which is definitly wrong because if sc fails v0 is set to 0 and previous value of -1 is overriden hence whole operation turns to bogus r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines bye bye. This is no longer referenced, but much code from it will resurface for a bus-space implementation. r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines Cavium-specific goo is no longer necessary here. Of course, I now have to write a bus space for cavium, but that shouldn't be too hard. r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines Move this to a more approrpiate plae. r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines Bring this in from the cavium port. r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines - Use restoreintr instead of enableint while accessing pcpu in DO_AST r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines - Add type cast for atomic_cmpset_acq_ptr arguments r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines - Remove now unused NetBSDism intr.h r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines - Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR macroses thet check if address belongs to KSEG0, KSEG1 or both of them respectively. r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines - Cast argument to proper type in order to avoid warnings like "shift value is too large for given type" r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines - Define accessor functions for CP0 Config(16) register selects 1, 2, 3. Content of these registers is defined in MIPS spec and can be used for obtaining info about CPU capabilities. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order. |
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