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| /freebsd-10.0-release/sys/dev/ste/ | ||
| H A D | if_stereg.h | diff 101493 Wed Aug 07 20:31:27 MDT 2002 ambrisko Fixes for the D-Link DFE-580 card. This is pretty much fixes any issue I can find: - Watchdog timeouts were due to starting the TX DMA engine before we had a packet ready for it. So the first packet sent never got out only if we sent more then one packet at a time did the others make it out and not blow up. Of course reseting the chip then caused us not to transmit the first packet again ie. catch-22. This required logic changes. - Combine interrupts on TX packets being queued up. - Don't keep running around the RX ring since we might get out of sync so only go around once per receive - Let the RX engine recover via the poll interface which is similar to the TX interface. This way the chip wakes up with no effort when we read enough packets. - Do better hand-shaking on RX & TX packets so they don't start of to soon. - Force a duplex setting when the link comes up after an ste_init or it will default to half-duplex and be really slow. This only happens on subsequent ste_init. The first one worked. - Don't call stat_update for every overflow. We only monitor the collisions so the tick interval is good enough for that. Just read in the collision stats to minimize bus reads. - Don't read the miibus every tick since it uses delays and delays are not good for performance. - Tie link events directly to the miibus code so the port gets set correctly if someone changes the port settings. - Reduce the extreme number of {R,T}FD's. They would consume 130K of kernel memory for each NIC. - Set the TX_THRESH to wait for the DMA engine to complete before running the TX FIFO. This hurts peak TX performance but under bi-directional load the DMA engine can't keep up with the FIFO. Testing shows that we end up in the case anyways (a la dc(4) issues but worse since the RX engine hogs everything). - When stopping the card do a reset since the reset verifies the card has stopped. Otherwise on heavy RX load the RX DMA engine is still stuffing packets into memory. If that happens after we free the DMA area memory bits get scribled in memory and bad things happen. This card still has seemingly unfixable issues under heavy RX load in which the card takes over the PCI bus. Sponsored by: Vernier Networks MFC after: 1 week |
| H A D | if_ste.c | diff 101493 Wed Aug 07 20:31:27 MDT 2002 ambrisko Fixes for the D-Link DFE-580 card. This is pretty much fixes any issue I can find: - Watchdog timeouts were due to starting the TX DMA engine before we had a packet ready for it. So the first packet sent never got out only if we sent more then one packet at a time did the others make it out and not blow up. Of course reseting the chip then caused us not to transmit the first packet again ie. catch-22. This required logic changes. - Combine interrupts on TX packets being queued up. - Don't keep running around the RX ring since we might get out of sync so only go around once per receive - Let the RX engine recover via the poll interface which is similar to the TX interface. This way the chip wakes up with no effort when we read enough packets. - Do better hand-shaking on RX & TX packets so they don't start of to soon. - Force a duplex setting when the link comes up after an ste_init or it will default to half-duplex and be really slow. This only happens on subsequent ste_init. The first one worked. - Don't call stat_update for every overflow. We only monitor the collisions so the tick interval is good enough for that. Just read in the collision stats to minimize bus reads. - Don't read the miibus every tick since it uses delays and delays are not good for performance. - Tie link events directly to the miibus code so the port gets set correctly if someone changes the port settings. - Reduce the extreme number of {R,T}FD's. They would consume 130K of kernel memory for each NIC. - Set the TX_THRESH to wait for the DMA engine to complete before running the TX FIFO. This hurts peak TX performance but under bi-directional load the DMA engine can't keep up with the FIFO. Testing shows that we end up in the case anyways (a la dc(4) issues but worse since the RX engine hogs everything). - When stopping the card do a reset since the reset verifies the card has stopped. Otherwise on heavy RX load the RX DMA engine is still stuffing packets into memory. If that happens after we free the DMA area memory bits get scribled in memory and bad things happen. This card still has seemingly unfixable issues under heavy RX load in which the card takes over the PCI bus. Sponsored by: Vernier Networks MFC after: 1 week |
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