| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/mips/ |
| H A D | sim-main.c | 52 address_translation(SIM_DESC sd, sim_cpu * cpu, address_word cia, address_word vAddr, int IorD, int LorS, address_word * pAddr, int *CCA, int raw) argument
90 prefetch(SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint) argument
124 load_memory(SIM_DESC SD, sim_cpu *CPU, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD) argument
243 store_memory(SIM_DESC SD, sim_cpu *CPU, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr) argument
404 cache_op(SIM_DESC SD, sim_cpu *CPU, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction) argument
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/mips/ |
| H A D | sim-main.c | 52 address_translation(SIM_DESC sd, sim_cpu * cpu, address_word cia, address_word vAddr, int IorD, int LorS, address_word * pAddr, int *CCA, int raw) argument
90 prefetch(SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint) argument
124 load_memory(SIM_DESC SD, sim_cpu *CPU, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD) argument
243 store_memory(SIM_DESC SD, sim_cpu *CPU, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr) argument
404 cache_op(SIM_DESC SD, sim_cpu *CPU, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction) argument
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/mips/ |
| H A D | sim-main.c | 52 address_translation(SIM_DESC sd, sim_cpu * cpu, address_word cia, address_word vAddr, int IorD, int LorS, address_word * pAddr, int *CCA, int raw) argument
90 prefetch(SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint) argument
124 load_memory(SIM_DESC SD, sim_cpu *CPU, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD) argument
243 store_memory(SIM_DESC SD, sim_cpu *CPU, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr) argument
404 cache_op(SIM_DESC SD, sim_cpu *CPU, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction) argument
[all...] |