Searched defs:getMatchingSuperReg (Results 1 - 2 of 2) sorted by relevance

/freebsd-11.0-release/contrib/llvm/lib/MC/
H A DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, function in class:MCRegisterInfo
/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp37 assert(SGPR32SetID < NumRegPressureSets && VGPR32SetID < NumRegPressureSets); } void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const { MCRegAliasIterator R(Reg, this, true); for (; R.isValid(); ++R) Reserved.set(*R); } unsigned SIRegisterInfo::reservedPrivateSegmentBufferReg( const MachineFunction &MF) const { const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>(); if (ST.hasSGPRInitBug()) { unsigned BaseIdx = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG - 8 - 4; unsigned BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx)); return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SReg_128RegClass); } if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { return AMDGPU::SGPR92_SGPR93_SGPR94_SGPR95; } return AMDGPU::SGPR96_SGPR97_SGPR98_SGPR99; } unsigned SIRegisterInfo::reservedPrivateSegmentWaveByteOffsetReg( const MachineFunction &MF) const { const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>(); if (ST.hasSGPRInitBug()) { unsigned Idx = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG - 6 - 1; return AMDGPU::SGPR_32RegClass.getRegister(Idx); } if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) argument

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