| /freebsd-10.1-release/contrib/llvm/lib/CodeGen/ |
| H A D | RegisterCoalescer.cpp | 82 const TargetRegisterInfo* TRI; member in class:__anon2291::RegisterCoalescer
1291 const TargetRegisterInfo *TRI; member in class:__anon2292::JoinVals
[all...] |
| H A D | MachineScheduler.cpp | 996 const TargetRegisterInfo *TRI; member in class:__anon2265::LoadClusterMutation
1619 const TargetRegisterInfo *TRI; member in class:__anon2268::GenericScheduler
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 274 GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF) argument
1205 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs, const TargetRegisterInfo *TRI) argument
[all...] |
| H A D | SelectionDAGISel.cpp | 396 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); local
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| H A D | SelectionDAG.cpp | 3736 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local
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| H A D | DAGCombiner.cpp | 7864 const TargetRegisterInfo *TRI = TLI.getTargetMachine().getRegisterInfo(); local
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| /freebsd-10.1-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 66 const TargetRegisterInfo *TRI; member in struct:__anon2451::ARMLoadStoreOpt
1548 const TargetRegisterInfo *TRI; member in struct:__anon2452::ARMPreAllocLoadStoreOpt
1591 IsSafeAndProfitableToMove(bool isLd, unsigned Base, MachineBasicBlock::iterator I, MachineBasicBlock::iterator E, SmallPtrSet<MachineInstr*, 4> &MemOps, SmallSet<unsigned, 4> &MemRegs, const TargetRegisterInfo *TRI) argument
[all...] |
| H A D | ARMBaseInstrInfo.cpp | 737 const TargetRegisterInfo *TRI = &getRegisterInfo(); local
1180 const TargetRegisterInfo *TRI = &getRegisterInfo(); local
1915 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo(); local
2281 const TargetRegisterInfo *TRI = &getRegisterInfo(); local
3233 getBundledDefMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist) argument
3257 getBundledUseMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &UseIdx, unsigned &Dist) argument
3975 getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, unsigned SReg, unsigned &Lane) argument
4005 getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, MachineInstr *MI, unsigned DReg, unsigned Lane, unsigned &ImplicitSReg) argument
4038 const TargetRegisterInfo *TRI = &getRegisterInfo(); local
[all...] |
| H A D | ARMISelLowering.cpp | 1790 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); local
|
| /freebsd-10.1-release/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 69 const HexagonRegisterInfo *TRI; member in struct:__anon2482::HexagonHardwareLoops
269 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0; local
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| H A D | HexagonISelDAGToDAG.cpp | 1223 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); local
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| H A D | HexagonISelLowering.cpp | 979 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); local
1002 const HexagonRegisterInfo *TRI = TM.getRegisterInfo(); local
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| /freebsd-10.1-release/contrib/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXAsmPrinter.cpp | 560 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); local
1668 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local
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| /freebsd-10.1-release/contrib/llvm/lib/Target/R600/ |
| H A D | AMDILCFGStructurizer.cpp | 181 const AMDGPURegisterInfo *TRI; member in class:__anon2564::AMDGPUCFGStructurizer
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| /freebsd-10.1-release/contrib/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfDebug.cpp | 1648 const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo(); local
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| /freebsd-10.1-release/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 917 const SparcRegisterInfo *TRI = local
1231 const SparcRegisterInfo *TRI = local
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| /freebsd-10.1-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 3561 const TargetRegisterInfo *TRI = &getRegisterInfo(); local
[all...] |
| H A D | X86ISelLowering.cpp | 2880 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); local
12114 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); local
14448 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); local
15264 checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, MachineBasicBlock* BB, const TargetRegisterInfo* TRI) argument
15324 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); local
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1548 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); local
2273 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); local
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| /freebsd-10.1-release/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 2281 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); local
2889 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); local
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| /freebsd-10.1-release/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 3447 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); local
6189 const PPCRegisterInfo *TRI = local
7673 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); local
|