Searched defs:Stage (Results 1 - 8 of 8) sorted by relevance
| /netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/MCA/Stages/ |
| H A D | Stage.h | 27 class Stage { class in namespace:llvm::mca
38 Stage() : NextInSequence(nullptr) {} function in class:llvm::mca::Stage
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | GCNSchedStrategy.h | 94 unsigned Stage; variable
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| /netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ModuloSchedule.h | 92 DenseMap<MachineInstr *, int> Stage; member in class:llvm::ModuloSchedule
105 ModuloSchedule(MachineFunction &MF, MachineLoop *Loop, std::vector<MachineInstr *> ScheduledInstrs, DenseMap<MachineInstr *, int> Cycle, DenseMap<MachineInstr *, int> Stage) argument
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| /netbsd-current/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | SubtargetEmitter.cpp | 305 const Record *Stage = StageList[i]; local
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | RegAllocGreedy.cpp | 241 LiveRangeStage Stage = RS_New; member in struct:__anon1858::RAGreedy::RegInfo
255 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { argument
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| H A D | ModuloSchedule.cpp | 1599 int Stage = getStage(MI); local
1778 unsigned Stage = Schedule.getNumStages() - 1 + I - J; local
1623 moveStageBetweenBlocks( MachineBasicBlock *DestBB, MachineBasicBlock *SourceBB, unsigned Stage) argument
1911 int Stage = getStage(MI); local
2139 parseSymbolString(StringRef S, int &Cycle, int &Stage) argument
2163 DenseMap<MachineInstr *, int> Cycle, Stage; local
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| /netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 458 enum InstrStage Stage; member in class:llvm::Instruction
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 435 unsigned Stage = II[SchedClass].LastStage - 1; local
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