| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVMergeBaseOffset.cpp | 138 Register Rs = TailAdd.getOperand(1).getReg(); local
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 109 RegisterSet &insert(const RegisterSet &Rs) { argument
112 RegisterSet &remove(const RegisterSet &Rs) { argument
[all...] |
| H A D | HexagonGenInsert.cpp | 129 RegisterSet &insert(const RegisterSet &Rs) { argument
132 RegisterSet &remove(const RegisterSet &Rs) { argument
[all...] |
| H A D | HexagonAsmPrinter.cpp | 409 MCOperand &Rs = Inst.getOperand(1); local
|
| H A D | HexagonSplitDouble.cpp | 147 const USet &Rs = I.second; local
375 Register Rs = MI->getOperand(1).getReg(); local
476 collectIndRegsForLoop(const MachineLoop *L, USet &Rs) argument
584 USet Rs; local
[all...] |
| H A D | HexagonConstExtenders.cpp | 293 Register Rs; member in struct:__anon5145::HexagonConstExtenders::ExtExpr
446 HCE::Register Rs; member in struct:__anon5145::PrintRegister
1504 Register Rs = ExtI.second.Rs; // Only one reg allowed now. local
1783 Register Rs = MI.getOperand(IsSub ? 3 : 2); local
[all...] |
| H A D | HexagonFrameLowering.cpp | 2407 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); local
[all...] |
| H A D | HexagonInstrInfo.cpp | 1236 Register Rs = Op2.getReg(); local
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCompound.cpp | 200 MCOperand Rs, Rt; local
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/ |
| H A D | MSP430Disassembler.cpp | 154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { argument
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); local
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); local
|
| /freebsd-12-stable/contrib/mandoc/ |
| H A D | mdoc.h | 152 struct mdoc_rs Rs; member in union:mdoc_data
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 1293 unsigned Rs = fieldFromInstruction(insn, 16, 5); local
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 636 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
650 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
675 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
705 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
748 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
778 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
819 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
858 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
900 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
945 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
987 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
1036 InsnType Rs = fieldFromInstruction(insn, 21, 5); local
1092 InsnType Rs = fieldFromInstruction(Insn, 21, 5); local
1134 InsnType Rs = fieldFromInstruction(Insn, 21, 5); local
1152 InsnType Rs = fieldFromInstruction(Insn, 21, 5); local
2561 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
2610 InsnType Rs = fieldFromInstruction(insn, 16, 5); local
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ScalarEvolution.cpp | 997 SmallVector<const SCEV *, 2> Qs, Rs; local
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1618 MCOperand &Rs = Inst.getOperand(2); local
1638 MCOperand &Rs = Inst.getOperand(2); local
1658 MCOperand &Rs = Inst.getOperand(2); local
1681 MCOperand &Rs = Inst.getOperand(1); local
1714 MCOperand &Rs = Inst.getOperand(1); local
1724 MCOperand &Rs = Inst.getOperand(1); local
1766 MCOperand &Rs = Inst.getOperand(1); local
1783 MCOperand &Rs = Inst.getOperand(1); local
1912 MCOperand &Rs = Inst.getOperand(1); local
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 3528 Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass); local
|
| /freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
| H A D | EmulateInstructionARM.cpp | 10166 uint32_t Rs = ReadCoreReg(s, &success); local
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1492 unsigned Rs = fieldFromInstruction(Val, 8, 4); local
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 4086 unsigned Rs = Inst.getOperand(0).getReg(); local
4099 unsigned Rs = Inst.getOperand(0).getReg(); local
|
| /freebsd-12-stable/contrib/binutils/gas/config/ |
| H A D | tc-arm.c | 8444 int Rd, Rs, Rn; local
8669 int Rd, Rs, Rn; local
8752 int Rd, Rs, Rn; local
10125 int Rd, Rs; local
[all...] |