| /freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/Disassembler/ |
| H A D | SystemZDisassembler.cpp | 50 decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned *Regs) argument
[all...] |
| /freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/ |
| H A D | RegisterScavenging.h | 180 void setUsed(BitVector &Regs) { argument
183 void setUnused(BitVector &Regs) { argument
|
| H A D | CallingConvLower.h | 281 unsigned getFirstUnallocated(const uint16_t *Regs, unsigned NumRegs) const { argument
308 unsigned AllocateReg(const uint16_t *Regs, unsigned NumRegs) { argument
320 unsigned AllocateReg(const uint16_t *Regs, const uint16_t *ShadowRegs, argument
|
| /freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCallingConvLower.h | 110 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { argument
137 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { argument
149 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, argument
|
| /freebsd-10-stable/contrib/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 68 GetGroupRegs( unsigned Group, std::vector<unsigned> &Regs, std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs) argument
[all...] |
| H A D | ExecutionDepsFix.cpp | 645 SmallVector<LiveReg, 4> Regs; local
|
| H A D | RegisterPressure.cpp | 422 void RegPressureTracker::addLiveRegs(ArrayRef<unsigned> Regs) { argument
|
| /freebsd-10-stable/contrib/llvm/utils/TableGen/ |
| H A D | CodeGenTarget.cpp | 222 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); local
|
| H A D | RegisterInfoEmitter.cpp | 171 const CodeGenRegister::Set &Regs = RC.getMembers(); local
314 EmitRegMappingTables(raw_ostream &OS, const std::vector<CodeGenRegister*> &Regs, bool isCtor) argument
440 EmitRegMapping(raw_ostream &OS, const std::vector<CodeGenRegister*> &Regs, bool isCtor) argument
708 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); local
1214 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); local
1306 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); local
[all...] |
| H A D | CodeGenRegisters.cpp | 159 RegUnitIterator(const CodeGenRegister::Set &Regs): argument
944 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); local
1235 CodeGenRegister::Set Regs; member in struct:__anon3861::UberRegSet
1266 const CodeGenRegister::Set &Regs = RegClass->getMembers(); local
1974 computeCoveredRegisters(ArrayRef<Record*> Regs) argument
[all...] |
| /freebsd-10-stable/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 607 SmallVector<unsigned, 4> Regs; member in struct:__anon252::RegsForValue
[all...] |
| /freebsd-10-stable/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 432 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { argument
442 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { argument
452 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, argument
[all...] |
| /freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 595 SmallVector<std::pair<unsigned,bool>, 4> Regs; local
667 SmallVector<unsigned, 4> Regs; local
[all...] |
| H A D | ARMLoadStoreOptimizer.cpp | 453 SmallVector<std::pair<unsigned, bool>, 8> Regs; local
286 MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, ArrayRef<std::pair<unsigned, bool> > Regs, ArrayRef<unsigned> ImpDefs) argument
[all...] |
| /freebsd-10-stable/contrib/llvm/lib/Target/R600/ |
| H A D | SIISelLowering.cpp | 312 SmallVector<SDValue, 4> Regs; local
|
| /freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 484 parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, bool IsAddress) argument
501 parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands, RegisterGroup Group, const unsigned *Regs, RegisterKind Kind) argument
520 parseAddress(unsigned &Base, const MCExpr *&Disp, unsigned &Index, const MCExpr *&Length, const unsigned *Regs, RegisterKind RegKind) argument
570 parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands, const unsigned *Regs, RegisterKind RegKind, MemoryKind MemKind) argument
[all...] |
| /freebsd-10-stable/contrib/llvm/lib/Transforms/Scalar/ |
| H A D | LoopStrengthReduce.cpp | 852 RateRegister(const SCEV *Reg, SmallPtrSet<const SCEV *, 16> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT) argument
900 RatePrimaryRegister(const SCEV *Reg, SmallPtrSet<const SCEV *, 16> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT, SmallPtrSet<const SCEV *, 16> *LoserRegs) argument
916 RateFormula(const TargetTransformInfo &TTI, const Formula &F, SmallPtrSet<const SCEV *, 16> &Regs, const DenseSet<const SCEV *> &VisitedRegs, const Loop *L, const SmallVectorImpl<int64_t> &Offsets, ScalarEvolution &SE, DominatorTree &DT, const LSRUse &LU, SmallPtrSet<const SCEV *, 16> *LoserRegs) argument
1192 SmallPtrSet<const SCEV *, 4> Regs; member in class:__anon2792::LSRUse
3775 SmallPtrSet<const SCEV *, 16> Regs; local
[all...] |
| /freebsd-10-stable/contrib/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2357 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs, argument
|