| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/NVPTX/ |
| H A D | NVPTXRegisterInfo.cpp | 305 getDwarfRegNum(unsigned RegNum, bool isEH) const { argument
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/ |
| H A D | MBlazeAsmPrinter.cpp | 137 unsigned RegNum = getMBlazeRegisterNumbering(Reg); local
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/ |
| H A D | MipsAsmPrinter.cpp | 159 unsigned RegNum = getMipsRegisterNumbering(Reg); local
174 unsigned RegNum = getMipsRegisterNumbering(Reg); local
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/ |
| H A D | X86RegisterInfo.cpp | 88 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const { argument
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 122 unsigned RegNum; member in union:__anon10190::CountValue::Values
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/AsmParser/ |
| H A D | MBlazeAsmParser.cpp | 91 unsigned RegNum; member in struct:__anon10202::MBlazeOperand::__anon10203::__anon10205
229 static MBlazeOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { argument
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| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/PowerPC/ |
| H A D | PPCCTRLoops.cpp | 135 unsigned RegNum; member in union:__anon10256::CountValue::Values
|
| H A D | PPCISelLowering.cpp | 1645 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); local
1673 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); local
[all...] |
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 1171 unsigned RegNum = GetX86RegNum(MO) << 4; local
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/ |
| H A D | ARMCodeEmitter.cpp | 1296 unsigned RegNum = II->getRegisterInfo().getEncodingValue(MO.getReg()); local
|
| H A D | ARMLoadStoreOptimizer.cpp | 485 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg); local
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 139 unsigned RegNum; member in struct:__anon10229::MipsOperand::__anon10230::__anon10232
224 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { argument
401 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum,StringRef Mnemonic) { argument
418 int RegNum = -1; local
[all...] |
| /macosx-10.10.1/llvmCore-3425.0.34/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 1276 unsigned RegNum = Registers[i]->EnumValue; local
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 342 unsigned RegNum; member in struct:__anon10144::ARMOperand::__anon10145::__anon10154
347 unsigned RegNum; member in struct:__anon10144::ARMOperand::__anon10145::__anon10155
376 unsigned RegNum; member in struct:__anon10144::ARMOperand::__anon10145::__anon10159
1406 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; local
2106 CreateCCOut(unsigned RegNum, SMLoc S) argument
2123 CreateReg(unsigned RegNum, SMLoc S, SMLoc E) argument
2208 CreateVectorList(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) argument
2219 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) argument
2231 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, bool isDoubleSpaced, SMLoc S, SMLoc E) argument
2283 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) argument
2468 unsigned RegNum = MatchRegisterName(lowerCase); local
[all...] |