| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPeephole.cpp | 240 Register Reg0 = Op0.getReg(); local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 224 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 312 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); local
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| H A D | ARMISelDAGToDAG.cpp | 2063 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2195 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2365 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2749 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2851 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2921 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
3262 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
3281 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
4958 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); local
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsMCCodeEmitter.cpp | 98 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); local
|
| H A D | MipsTargetStreamer.cpp | 166 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, argument
175 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, argument
185 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, argument
190 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument
205 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, argument
217 emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
223 emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, MCOperand Op3, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
236 emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
242 emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI) argument
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 463 unsigned Reg0 = local
481 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); local
|
| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 739 uint16_t Reg0 = 0; member in class:llvm::MCRegUnitRootIterator
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 783 buildEXP(const TargetInstrInfo &TII, MachineInstr *Insert, unsigned Tgt, unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3, unsigned VM, bool Compr, unsigned Enabled, bool Done) argument
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 395 Register Reg0 = MI.getOperand(0).getReg(); local
425 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); local
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 174 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); local
|
| H A D | RegisterCoalescer.cpp | 2502 unsigned Reg0; local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 523 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); local
536 Register Reg0 = MBBI->getOperand(1).getReg(); local
574 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); local
585 Register Reg0 = MBBI->getOperand(0).getReg(); local
[all...] |
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 968 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) { argument
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 2055 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0); local
2086 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0); local
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| H A D | X86InstrInfo.cpp | 4945 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); local
|