| /freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86CallFrameOptimization.cpp | 297 unsigned int Reg = MO.getReg(); local
408 unsigned int Reg = MO.getReg(); local
477 unsigned int Reg = PushOp.getReg(); local
524 canFoldIntoRegPush( MachineBasicBlock::iterator FrameSetup, unsigned Reg) argument
[all...] |
| H A D | X86MachineFunctionInfo.h | 135 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
138 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
|
| /freebsd-11.0-release/contrib/llvm/tools/llvm-readobj/ |
| H A D | Win64EHDumper.cpp | 73 static StringRef getUnwindRegisterName(uint8_t Reg) { argument
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| /freebsd-11.0-release/contrib/llvm/include/llvm/Target/ |
| H A D | TargetRegisterInfo.h | 282 static bool isStackSlot(unsigned Reg) { argument
287 static int stackSlot2Index(unsigned Reg) { argument
300 isPhysicalRegister(unsigned Reg) argument
307 isVirtualRegister(unsigned Reg) argument
314 virtReg2Index(unsigned Reg) argument
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 355 unsigned Reg = RegInfo.createVirtualRegister(RC); local
373 unsigned Reg = 0; local
391 unsigned Reg = 0; local
527 unsigned Reg local
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/CodeGen/ |
| H A D | MachineCSE.cpp | 128 unsigned Reg = MO.getReg(); local
174 MachineCSE::isPhysDefTriviallyDead(unsigned Reg, argument
224 unsigned Reg = MO.getReg(); local
242 unsigned Reg = MO.getReg(); local
360 isProfitableToCSE(unsigned CSReg, unsigned Reg, MachineInstr *CSMI, MachineInstr *MI) argument
[all...] |
| H A D | MachineRegisterInfo.cpp | 40 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument
46 MachineRegisterInfo::constrainRegClass(unsigned Reg, argument
63 MachineRegisterInfo::recomputeRegClass(unsigned Reg) { argument
97 unsigned Reg local
110 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
[all...] |
| H A D | MachineSink.cpp | 195 MachineSinking::AllUsesDominatedByBlock(unsigned Reg, argument
376 unsigned Reg = MO.getReg(); local
496 isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, MachineBasicBlock *MBB, MachineBasicBlock *SuccToSinkTo, AllSuccsCache &AllSuccessors) argument
603 unsigned Reg = MO.getReg(); local
718 unsigned Reg = MO.getReg(); local
[all...] |
| H A D | PHIElimination.cpp | 561 unsigned Reg = BBI->getOperand(i).getReg(); local
626 bool PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock *MBB) { argument
635 isLiveOutPastPHIs(unsigned Reg, const MachineBasicBlock *MBB) argument
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 382 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) { argument
|
| H A D | SelectionDAGBuilder.cpp | 601 RegsForValue(LLVMContext &Context, const TargetLowering &TLI, const DataLayout &DL, unsigned Reg, Type *Ty) argument
[all...] |
| /freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/ |
| H A D | MachineTraceMetrics.h | 121 unsigned Reg; member in struct:llvm::MachineTraceMetrics::LiveInReg
127 LiveInReg(unsigned Reg, unsigned Height = 0) : Reg(Reg), Height(Height) {} argument
|
| /freebsd-11.0-release/contrib/llvm/lib/MC/MCParser/ |
| H A D | COFFAsmParser.cpp | 601 unsigned Reg = 0; local
614 unsigned Reg = 0; local
655 unsigned Reg = 0; local
682 unsigned Reg local
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 549 int Reg = scavengeRegister(G, C, MBB); local
725 getColor(unsigned Reg) argument
[all...] |
| H A D | AArch64AsmPrinter.cpp | 191 unsigned Reg = MO.getReg(); local
218 unsigned Reg = MO.getReg(); local
243 unsigned Reg local
273 unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR; local
315 unsigned Reg = MO.getReg(); local
[all...] |
| H A D | AArch64ConditionalCompares.cpp | 223 unsigned Reg = I.getOperand(oi).getReg(); local
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 119 unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i); local
546 unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg, argument
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 142 unsigned Reg = MO.getReg(); local
201 unsigned Reg = MO.getReg(); local
382 unsigned Reg = MI->getOperand(I).getReg(); local
430 createDupLane(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned Reg, unsigned Lane, bool QPR) argument
533 optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) argument
[all...] |
| H A D | MLxExpansionPass.cpp | 90 unsigned Reg = MI->getOperand(1).getReg(); local
118 unsigned Reg = MI->getOperand(0).getReg(); local
144 unsigned Reg = MI->getOperand(1).getReg(); local
185 hasRAWHazard(unsigned Reg, MachineInstr *MI) const argument
[all...] |
| H A D | Thumb1FrameLowering.cpp | 147 unsigned Reg = CSI[i].getReg(); local
208 unsigned Reg = I->getReg(); local
587 unsigned Reg = CSI[i-1].getReg(); local
628 unsigned Reg = CSI[i-1].getReg(); local
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 206 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo); local
218 unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo); local
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/XCore/ |
| H A D | XCoreFrameLowering.cpp | 52 unsigned Reg; member in struct:__anon3098::StackSlotInfo
433 unsigned Reg = it->getReg(); local
463 unsigned Reg = it->getReg(); local
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonAsmPrinter.cpp | 73 inline static unsigned getHexagonRegisterPair(unsigned Reg, argument
278 MCOperand &Reg = MappedInst.getOperand(0); local
297 MCOperand &Reg = MappedInst.getOperand(0); local
322 unsigned Reg = RI->getEncodingValue(Rt.getReg()); local
333 unsigned Reg local
345 unsigned Reg = RI->getEncodingValue(Rt.getReg()); local
357 unsigned Reg = RI->getEncodingValue(Rs.getReg()); local
539 unsigned Reg = RI->getEncodingValue(Rt.getReg()); local
[all...] |
| H A D | HexagonBitTracker.cpp | 78 BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const { argument
[all...] |
| H A D | HexagonCopyToCombine.cpp | 188 static bool isEvenReg(unsigned Reg) { argument
359 unsigned Reg = Op.getReg(); local
387 unsigned Reg = Op.getReg(); local
[all...] |