| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | LiveStacks.cpp | 57 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument
82 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local
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| H A D | RegAllocBase.cpp | 127 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg()); local
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| H A D | RegisterClassInfo.cpp | 172 const TargetRegisterClass *RC = nullptr; local
[all...] |
| H A D | AggressiveAntiDepBreaker.h | 48 const TargetRegisterClass *RC; member in struct:llvm::AggressiveAntiDepState::RegisterReference
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| H A D | MIRVRegNamerUtils.cpp | 169 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); local
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyReplacePhysRegs.cpp | 86 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg); local
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| H A D | WebAssemblyRegColoring.cpp | 140 const TargetRegisterClass *RC = MRI->getRegClass(Old); local
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86FixupSetCC.cpp | 101 const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit() local
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreMachineFunctionInfo.cpp | 38 const TargetRegisterClass &RC = XCore::GRRegsRegClass; local
56 const TargetRegisterClass &RC = XCore::GRRegsRegClass; local
69 const TargetRegisterClass &RC = XCore::GRRegsRegClass; local
[all...] |
| /netbsd-current/common/lib/libc/hash/sha3/ |
| H A D | keccak.c | 156 static const uint64_t RC[24] = { local
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXRegisterInfo.cpp | 28 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { argument
72 getNVPTXRegClassStr(TargetRegisterClass const *RC) argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRegPressure.cpp | 75 const auto RC = MRI.getRegClass(Reg); local
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| H A D | AMDGPUISelLowering.h | 283 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) const argument
290 CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) const argument
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| H A D | SIPreAllocateWWMRegs.cpp | 159 const TargetRegisterClass *RC = TRI->getPhysRegClass(PhysReg); local
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64DeadRegisterDefinitionsPass.cpp | 160 const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF); local
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXCopy.cpp | 51 bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC, argument
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegisterBank.cpp | 35 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); local
105 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); local
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | BitTracker.cpp | 115 raw_ostream &operator<<(raw_ostream &OS, const BT::RegisterCell &RC) { argument
165 OS << "]:" << RC[Start]; local
201 bool BT::RegisterCell::meet(const RegisterCell &RC, Registe argument
214 insert(const BT::RegisterCell &RC, const BitMask &M) argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | Thumb1InstrInfo.cpp | 79 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
107 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsMachineFunction.cpp | 71 const TargetRegisterClass *RC; local
152 const TargetRegisterClass &RC = local
167 const TargetRegisterClass &RC = Mips::GPR32RegClass; local
193 getMoveF64ViaSpillFI(MachineFunction &MF, const TargetRegisterClass *RC) argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | FastISelEmitter.cpp | 36 const CodeGenRegisterClass *RC; member in struct:__anon3296::InstructionMemo
41 InstructionMemo(StringRef Name, const CodeGenRegisterClass *RC, argument
[all...] |
| /netbsd-current/crypto/external/bsd/openssl.old/dist/crypto/whrlpool/ |
| H A D | wp_block.c | 480 #define RC (&(Cx.q[256*N])) macro
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| /netbsd-current/crypto/external/bsd/openssl/dist/crypto/whrlpool/ |
| H A D | wp_block.c | 486 #define RC (&(Cx.q[256*N])) macro
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 235 AArch64RegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, argument
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.cpp | 124 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
147 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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