| /freebsd-11.0-release/contrib/llvm/lib/Target/XCore/ |
| H A D | XCoreMachineFunctionInfo.cpp | 38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/CodeGen/ |
| H A D | LiveStackAnalysis.cpp | 60 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument
84 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local
|
| H A D | AggressiveAntiDepBreaker.h | 43 const TargetRegisterClass *RC; member in struct:llvm::AggressiveAntiDepState::__anon2431
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| H A D | RegisterClassInfo.cpp | 157 const TargetRegisterClass *RC = nullptr; local
[all...] |
| H A D | CriticalAntiDepBreaker.cpp | 613 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] local
375 findSuitableFreeRegister(RegRefIter RegRefBegin, RegRefIter RegRefEnd, unsigned AntiDepReg, unsigned LastNewReg, const TargetRegisterClass *RC, SmallVectorImpl<unsigned> &Forbid) argument
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| /freebsd-11.0-release/contrib/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.cpp | 45 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
63 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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| /freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
| H A D | BitTracker.cpp | 105 raw_ostream &llvm::operator<<(raw_ostream &OS, const BT::RegisterCell &RC) { argument
155 OS << "]:" << RC[Start]; local
184 bool BT::RegisterCell::meet(const RegisterCell &RC, unsigne argument
198 insert(const BT::RegisterCell &RC, const BitMask &M) argument
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsMachineFunction.cpp | 41 const TargetRegisterClass *RC = local
62 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; local
68 const TargetRegisterClass *RC = local
83 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local
106 getMoveF64ViaSpillFI(const TargetRegisterClass *RC) argument
[all...] |
| H A D | Mips16RegisterInfo.cpp | 60 saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const argument
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| H A D | MipsRegisterInfo.cpp | 59 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, argument
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| /freebsd-11.0-release/contrib/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXRegisterInfo.cpp | 29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { argument
51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { argument
[all...] |
| /freebsd-11.0-release/crypto/openssl/crypto/whrlpool/ |
| H A D | wp_block.c | 461 #define RC (&(Cx.q[256*N])) macro
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerI1Copies.cpp | 91 const TargetRegisterClass *RC = MRI.getRegClass(Reg); local
|
| H A D | SIRegisterInfo.h | 84 static bool isPseudoRegClass(const TargetRegisterClass *RC) { argument
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | Thumb1InstrInfo.cpp | 71 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
97 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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| H A D | Thumb2InstrInfo.cpp | 125 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
166 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...] |
| H A D | ThumbRegisterInfo.cpp | 44 ThumbRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, argument
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| /freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXCopy.cpp | 57 bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC, argument
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| /freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrInfo.cpp | 42 const TargetRegisterClass *RC = TargetRegisterInfo::isVirtualRegister(DestReg) ? local
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| H A D | WebAssemblyRegColoring.cpp | 139 const TargetRegisterClass *RC = MRI->getRegClass(Old); local
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| /freebsd-11.0-release/contrib/llvm/utils/TableGen/ |
| H A D | FastISelEmitter.cpp | 37 const CodeGenRegisterClass *RC; member in struct:__anon4596::InstructionMemo
[all...] |
| /freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 119 getMinCost(const TargetRegisterClass *RC) argument
127 getLastCostChange(const TargetRegisterClass *RC) argument
[all...] |
| /freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | SIMCCodeEmitter.cpp | 204 const MCRegisterClass &RC = MRI.getRegClass(RCID); local
266 const MCRegisterClass &RC = MRI.getRegClass(RCID); local
|
| /freebsd-11.0-release/contrib/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.cpp | 37 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
64 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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| /freebsd-11.0-release/contrib/llvm/tools/clang/lib/AST/ |
| H A D | RawCommentList.cpp | 272 void RawCommentList::addComment(const RawComment &RC, argument
|