| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 330 bool HexagonBitSimplify::isZero(const BitTracker::RegisterCell &RC, argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsOptimizePICCall.cpp | 139 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg); local
|
| H A D | Mips16ISelDAGToDAG.cpp | 76 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; local
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 215 unsigned RC; local
|
| H A D | SparcInstrInfo.cpp | 395 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
434 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZHazardRecognizer.cpp | 123 const TargetRegisterClass *RC = TII->getRegClass(MID, OpIdx, TRI, MF); local
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMCInstLower.cpp | 210 static wasm::ValType getType(const TargetRegisterClass *RC) { argument
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.cpp | 347 RISCVRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, argument
|
| /netbsd-current/external/apache2/llvm/dist/llvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/ |
| H A D | RemoteJITUtils.cpp | 236 int RC = execvp(ExecPath.get(), Args); local
|
| /netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/MIRParser/ |
| H A D | MIParser.h | 41 const TargetRegisterClass *RC; member in union:llvm::VRegInfo::__anon1439
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerSGPRSpills.cpp | 98 const TargetRegisterClass *RC = local
137 const TargetRegisterClass *RC = local
222 const TargetRegisterClass *RC = local
|
| H A D | GCNDPPCombine.cpp | 363 const TargetRegisterClass *RC = MRI->getRegClass(MovDst->getReg()); local
481 const TargetRegisterClass *RC = MRI->getRegClass(DPPMovReg); local
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 178 ARMRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, argument
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86PreTileConfig.cpp | 232 const TargetRegisterClass *RC = TRI->getRegClass(X86::TILERegClassID); local
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.cpp | 358 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
381 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
|
| /netbsd-current/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | RegisterBankEmitter.cpp | 73 void addRegisterClass(const CodeGenRegisterClass *RC) { argument
169 visitRegisterBankClasses( const CodeGenRegBank &RegisterClassHierarchy, const CodeGenRegisterClass *RC, const Twine &Kind, std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn, SmallPtrSetImpl<const CodeGenRegisterClass *> &VisitedRCs) argument
246 const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegsSize(); local
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | DetectDeadLanes.cpp | 251 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); local
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 540 getCatchPadExceptionPointerVReg( const Value *CPI, const TargetRegisterClass *RC) argument
|
| /netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 291 isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const argument
299 isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const argument
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64SIMDInstrOpt.cpp | 90 const TargetRegisterClass RC; member in struct:__anon2153::AArch64SIMDInstrOpt::InstReplInfo
355 const TargetRegisterClass *RC = &AArch64::FPR128RegClass; local
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 162 const MCRegisterClass &RC = MRI.getRegClass(RCE.RegisterClassID); local
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 100 const TargetRegisterClass *RC; local
416 const TargetRegisterClass *RC local
567 const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front()); local
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | InlineAsm.h | 303 static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) { argument
354 static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) { argument
|
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | CGSCCPassManager.cpp | 201 LazyCallGraph::RefSCC *RC = RCWorklist.pop_back_val(); local
897 RefSCC *RC = &InitialRC; local
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfExpression.cpp | 137 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg); local
|