/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
H A D | AVRAsmPrinter.cpp | 114 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); local
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H A D | AVRInstrInfo.cpp | 120 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 159 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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H A D | AVRRegisterInfo.cpp | 86 AVRRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
H A D | InstructionSelect.cpp | 251 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); local
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | SwiftErrorValueTracking.cpp | 36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); local 58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); local 126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); local 241 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); local
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H A D | RDFRegisters.cpp | 176 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; local [all...] |
H A D | CriticalAntiDepBreaker.cpp | 633 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] local 396 findSuitableFreeRegister(RegRefIter RegRefBegin, RegRefIter RegRefEnd, unsigned AntiDepReg, unsigned LastNewReg, const TargetRegisterClass *RC, SmallVectorImpl<unsigned> &Forbid) argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyInstrInfo.cpp | 63 const TargetRegisterClass *RC = local
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H A D | WebAssemblyExplicitLocals.cpp | 88 static unsigned getDropOpcode(const TargetRegisterClass *RC) { argument 107 static unsigned getLocalGetOpcode(const TargetRegisterClass *RC) { argument 126 getLocalSetOpcode(const TargetRegisterClass *RC) argument 145 getLocalTeeOpcode(const TargetRegisterClass *RC) argument 164 typeForRegClass(const TargetRegisterClass *RC) argument 273 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); local 306 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); local 378 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ThumbRegisterInfo.cpp | 43 ThumbRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, argument
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H A D | Thumb2InstrInfo.cpp | 164 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 207 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitTracker.cpp | 92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); local 130 composeWithSubRegIndex( const TargetRegisterClass &RC, unsigned Idx) const argument [all...] |
H A D | HexagonGenPredicate.cpp | 140 const TargetRegisterClass *RC = MRI->getRegClass(R); local 436 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R); local
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsRegisterInfo.cpp | 67 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, argument
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H A D | Mips16RegisterInfo.cpp | 56 saveScavengerRegister( MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 36 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 63 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86RegisterBankInfo.cpp | 44 X86RegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, argument [all...] |
/netbsd-current/external/bsd/pkg_install/dist/lib/ |
H A D | dewey.c | 52 RC = -1, enumerator in enum:__anon10
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 136 const TargetRegisterClass *RC = nullptr; local 211 const TargetRegisterClass *RC = local 281 const TargetRegisterClass *RC = TLI->getRegClassFor( local [all...] |
H A D | ScheduleDAGSDNodes.cpp | 133 const TargetRegisterClass *RC = local
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H A D | ResourcePriorityQueue.cpp | 482 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); local 493 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); local [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
H A D | ARCFrameLowering.cpp | 440 const TargetRegisterClass *RC = &ARC::GPR32RegClass; local
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H A D | ARCInstrInfo.cpp | 293 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 322 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | RegisterBankInfo.h | 604 getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const { argument
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
H A D | M68kRegisterInfo.cpp | 93 const TargetRegisterClass *RC = *I; local
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