/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 381 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass local 413 const TargetRegisterClass *RC = Is64Bit ? local 1318 const TargetRegisterClass *RC = local 1360 const TargetRegisterClass *RC; local 1404 const TargetRegisterClass *RC = local 1445 const TargetRegisterClass *RC = nullptr; local 1668 const TargetRegisterClass *RC; local 1719 const TargetRegisterClass *RC; local 1819 const TargetRegisterClass *RC; local 2675 const TargetRegisterClass *RC; local 2973 const TargetRegisterClass *RC; local 4046 const TargetRegisterClass *RC = local 4080 const TargetRegisterClass *RC = local 4105 const TargetRegisterClass *RC = local 4182 const TargetRegisterClass *RC = local 4208 const TargetRegisterClass *RC = local 4298 const TargetRegisterClass *RC = local 4324 const TargetRegisterClass *RC = local 4446 const TargetRegisterClass *RC = local 4629 const TargetRegisterClass *RC = local 4816 const TargetRegisterClass *RC = nullptr; local 4910 const TargetRegisterClass *RC; local [all...] |
H A D | AArch64FrameLowering.cpp | 3403 const TargetRegisterClass &RC = AArch64::GPR64RegClass; local 3468 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); local
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H A D | AArch64ISelDAGToDAG.cpp | 559 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64); local 4238 auto RC = CurDAG->getTargetConstant(AArch64::ZPRRegClassID, DL, MVT::i64); local 4267 auto RC = CurDAG->getTargetConstant(AArch64::ZPRRegClassID, DL, MVT::i64); local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelDAGToDAG.cpp | 565 SDValue RC, SubReg0, SubReg1; local 2983 auto RC = Lo->isDivergent() ? AMDGPU::VReg_64RegClassID local 3489 const TargetRegisterClass *RC local [all...] |
H A D | AMDGPURegisterBankInfo.cpp | 287 AMDGPURegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, argument
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H A D | AMDGPUInstructionSelector.cpp | 89 const TargetRegisterClass *RC = local 140 const TargetRegisterClass *RC local 189 const TargetRegisterClass *RC = local 201 const TargetRegisterClass *RC local 366 const TargetRegisterClass &RC local 699 const auto &RC = local 786 const TargetRegisterClass *RC = TRI.getConstrainedRegClassForOperand(MO, *MRI); local 1533 const TargetRegisterClass *RC local 2634 const TargetRegisterClass *RC = IsSgpr ? local 3518 const TargetRegisterClass &RC = local [all...] |
H A D | AMDGPUISelLowering.cpp | 5237 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT, const SDLoc &SL, bool RawReg) const argument 5308 loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const argument
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H A D | SIISelLowering.cpp | 1911 const TargetRegisterClass *RC; local 2076 const TargetRegisterClass *RC; local 2253 allocateSGPR32InputImpl(CCState &CCInfo, const TargetRegisterClass *RC, unsigned NumArgRegs) argument 2273 allocateFixedSGPRInputImpl(CCState &CCInfo, const TargetRegisterClass *RC, MCRegister Reg) argument 2483 const TargetRegisterClass *RC = local 2705 const TargetRegisterClass *RC = nullptr; local 2917 const TargetRegisterClass *RC = MRI.getRegClass(VReg); local 2981 const TargetRegisterClass *RC = nullptr; local [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 957 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument 1005 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument 1738 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg()); local [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 5772 unsigned RC; local
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H A D | ARMBaseInstrInfo.cpp | 1115 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument 1372 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/M68k/ |
H A D | M68kISelLowering.cpp | 947 const TargetRegisterClass *RC; local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchISelLowering.cpp | 3274 const TargetRegisterClass *RC = &LoongArch::LASX256RegClass; local 3754 const TargetRegisterClass *RC = TLI.getRegClassFor(LocVT.getSimpleVT()); local 3918 const TargetRegisterClass *RC = &LoongArch::GPRRegClass; local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 1261 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) argument 1646 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); local 1665 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); local 1861 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); local 1913 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); local 4049 const TargetRegisterClass *RC; local 4387 const TargetRegisterClass *RC = getRegClassFor(RegTy); local 4506 const TargetRegisterClass *RC = getRegClassFor(RegTy); local [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachinePipeliner.cpp | 426 auto *RC = MRI.getRegClass(DefOp.getReg()); local
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/freebsd-current/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineAndOrXor.cpp | 3995 const APInt *LC, *RC; local
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/freebsd-current/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | GlobalISelMatchTable.h | 1070 const CodeGenRegisterClass &RC; member in class:llvm::RegisterBankOperandMatcher 2377 const CodeGenRegisterClass &RC; member in class:llvm::ConstrainOperandToRegClassAction 1073 RegisterBankOperandMatcher(unsigned InsnVarID, unsigned OpIdx, const CodeGenRegisterClass &RC) argument 2380 ConstrainOperandToRegClassAction(unsigned InsnID, unsigned OpIdx, const CodeGenRegisterClass &RC) argument
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 4914 SDValue RC = CurDAG->getTargetConstant(RegClass, dl, MVT::i32); local 4952 SDValue RC = CurDAG->getTargetConstant(RegClass, dl, MVT::i32); local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 6403 unsigned MipsAsmParser::getReg(int RC, int RegNo) { argument
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 1246 parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC, argument 1603 const TargetRegisterClass *RC; local 1748 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass; local 8601 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass; local 8892 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass; local 9126 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass; local 9228 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); local [all...] |
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 2693 const MCRegisterClass RC = TRI->getRegClass(RCID); local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 4483 const MCRegisterClass *RC; local 4873 const MCRegisterClass *RC = (Spacing == 1) ? local [all...] |
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetLowering.h | 982 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; local 1003 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; local 2442 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) { argument
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/freebsd-current/contrib/llvm-project/clang/lib/AST/ |
H A D | ASTContext.cpp | 325 void ASTContext::addComment(const RawComment &RC) { argument 573 const RawComment *RC = getRawCommentForDeclNoCache(D); local 599 const RawComment *RC = getRawCommentForAnyRedecl(D, &OriginalDecl); local
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/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.cpp | 1023 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); local 9098 const TargetRegisterClass *RC; local 9519 const TargetRegisterClass *RC = local [all...] |