Searched defs:PCIEIP_REG_VENDOR_SPECIFIC_REG1_BB (Results 1 - 1 of 1) sorted by relevance

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2236 #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_BB 0x000188UL //Access:RW DataWidth:0x20 // If bit 0 of the EXT_CAP_ENA for EP or bit 0 of RC_EXT_CAP_ENA for RC is reset to '0', reading this register will return all 0's. By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining VendorCapOn or PCIE_VF_BAR_STRIDE in version.v macro
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