Searched defs:PCIEIP_REG_SD_EQ_STATUS1_REG_K2 (Results 1 - 1 of 1) sorted by relevance

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h3981 #define PCIEIP_REG_SD_EQ_STATUS1_REG_K2 0x00036cUL //Access:R DataWidth:0x20 // Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The following fields are available when Equalization finished unsuccessfully(EQ_CONVERGENCE_INFO=2). - EQ_RULEA_VIOLATION - EQ_RULEB_VIOLATION - EQ_RULEC_VIOLATION - EQ_REJECT_EVENT For more details, see the RAS DES section in the Core Operations chapter of the Databook. macro
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