Searched defs:PCIEIP_REG_SD_EQ_CONTROL1_REG_K2 (Results 1 - 1 of 1) sorted by relevance

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h3936 #define PCIEIP_REG_SD_EQ_CONTROL1_REG_K2 0x00035cUL //Access:RW DataWidth:0x20 // Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport registers. For more details, see the RAS DES section in the Core Operations chapter of the Databook. macro
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