Searched defs:PCIEIP_REG_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_K2 (Results 1 - 1 of 1) sorted by relevance

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h3937 #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_K2 (0xf<<0) // EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky. macro
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