Searched defs:PCIEIP_REG_REG_ROOT_CAP_RC_EXT2_CAP_ENA_BB (Results 1 - 1 of 1) sorted by relevance

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h4966 #define PCIEIP_REG_REG_ROOT_CAP_RC_EXT2_CAP_ENA_BB (0x1f<<3) // If it is set, indicates RC supports CLKREQ Enable for the RC extended capability structures. Basic extended capability structure is defined in bits 31:30 of RC_EXT_CAP_ENA field . AER in bits 31:30 is always enabled, so that extended capability structure will follow the requirement of starting at 0x100. L1Sub capability will be present only if PMCR_RC_L1_SUBSTATES_ENA is defined in version.v Secondary PCIE extended capability will be present only if pcieGen3Rate is defined in version.v macro
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